EEVblog Electronics Community Forum
Electronics => Beginners => Topic started by: fatlimey on October 15, 2009, 12:51:32 am
-
Hello, love your show!
I'm an enthusiastic beginner, blown up my fair share of parts poking around, but I do love putting together kits that other people have designed. Learning how they work and, more importantly, how they came to design it that way in the first place.
While assembling kits I have diligently added decoupling capacitors wherever the design says so, but I have absolutely no idea how one goes about working out where to put them and what size to use. How do the designers know "Ah, a 200pf right... here will do the trick"? Are they just guessing? Poking around until the weirdness disappears? That might work on a small device, but then how do these things get done on large PCBs like CPU motherboards?
It seems like a black art to me, especially on digital circuitry. I fully understand digital logic but what kind of mindset helps you look at digital devices also as analog devices?
Thanks for any insight you have,
- Fatlimey,.
-
I usually add them following datasheet specifications. They usually tell you where to put caps and their values. I then add a bunch of caps on the supply, within the limit of the regulator, just to be sure. Usually, when you know your signals, you will know if you have spikes to damp and choose your own cap based on the input impedance and such. ;)
-
Once you get into higher frequencies (above DC) any inductance or capacitance acts like a resistance. The inductance of the long path back to your supply causes voltage drops when there are switching transients in the digital IC, just as the resistance of a long wire would cause a voltage drop when supplying some distant load.
Decoupling capacitors "bypass" the longer more inductive lines back to your supply; rather than the current running in a loop right back up to your power supply, they allow it to run in a much smaller loop out of your chip and through the capacitor.
The impedance of a capacitor is frequency dependant, and decreases with frequency (the "resistance" of a capacitor near DC is very high--like an open circuit). So you need a high value that has a sufficiently low impedance to cover the lower frequencies. These tend to be "bulk" values (uF range). The problem then is that at a certain point, the parasitic inductance of a large value capacitor starts to _increase_ the impedance at higher frequencies. The solution is to parallel another capacitor of a lower value. That's why as clock speeds get higher you see more de-coupling capacitors at differing values.
The other thing that helps most high speed boards is the capacitance of the supply and ground planes in the PCB.
If you want to learn about the actual values you'd need to use, or more about the subject in general, you need one of:
http://www.amazon.com/Signal-Power-Integrity-Simplified-2nd/dp/0132349795
http://www.amazon.com/exec/obidos/tg/detail/-/013141884X
http://www.amazon.com/High-Speed-Digital-Design-Handbook/dp/0133957241
The first two would be good for a beginner (even a non-engineer). The third one is a classic, but there is a new edition coming out soon.
There are some notes online from the second book online:
http://www.ultracad.com/article_outline.htm
In particular:
http://www.ultracad.com/mentor/esr%20and%20bypass%20caps.pdf
But you may want to read the introduction sections of one of the first two books before tackling the details.
-
Thank you.
Looks like I've got me some new bedtime reading!
- Fatlimey.
-
Ian has covered it well.
But the basic answer is that, in general, when it comes to decoupling capacitors we just pretty much pick the value out of the air.
Why? Well it's extremely difficult, if not impossible to accurately calculate sometimes, and it's not actually going to matter too much as whole range of value will do the same job. There are so many interacting variables like lead inductance, trace resistance/inductance, plane capacitance/resistance/inductance, and the list goes on. Some people try and model it, but most just throw in a value they know will roughly work based on experience.
So when you see a 100nF decoupling cap, there is no major reason for that value, apart from it being in a rough ballpack and a nice round figure. How about an oddball value like 2.2nF ? Well, maybe it's just because they have used that value elsewhere on the board, so it was convenient and they needed something smaller than a standard 100nF. You get the idea!
Often you just need "something" there, and the actual value doesn't really matter to a point.
Yes, we also "poke around until the weirdness/problem disappears"!
Say your prototype works but doesn't pass some EMI test (radiating too much noise). You might throw a few caps around and see how it changes, usually you'll nail it on the first few goes. Trying to calculate and model the whole system could take years and an entire PhD thesis! So you just throw a cap here or there (once again based on experience of the likely culprit) until you fix it. Then you measure the performance you are interested in to make sure it's all hunky-dory.
And yes, follow the manufacturers datasheet or app note recommendations is the usual way to go. Where do they get their value from?, see above! A lot of electronics is "warm and fuzzy", not the clinical calculated ideal stuff you learn in school.
It's not all like that of course, there are times when you need to accurately calculate values like this for some apps.
Dave.
-
for large powerful supplies caps are put in paralel so that the overall capacitance reacts faster (charging and discharging), for large cicuits its a general rule to use a 100 uF and a 100 nF in paralel as physically close as possible to the supply pins of each IC, a good experiment is to set up a pic using the PWM output and have a set output, power the pic's board/breadboard from a long wire say 2 metres, now use different decoupling caps and whatch the change in the quality of the output waveform on a scope, this may work with a 555 in astable mode but don't quote me on it
-
Very cool to see the "real world" approach vs. theory. I've worked in software for 15 years and the same BS is used to get crap out the door. There's theory, and then there's real-world "Get-R-Done" principles. For me, I'm happy to know where those real-world solutions trump the endless theory that would otherwise leave me stuck in some book for weeks before I would feel competant enough to get on with the design -- thanks Dave!
-
I'm afraid that there is lots of theory that cannot be applied and taken on face value, there will always be physical/practical implications because we live in a real world
-
The size of the decoupling capacitor is dependent on the speed the chip ACTUALLY operates. If you have an IC that is only operating at 1Mhz but is capable of operating at 100MHz you will find that the outputs will change state at the speed required for 100MHz operation. This will require capacitors that can react to this. Generally what you will find is that you will have a large capacitor for general decoupling (100uF) and a one or more smaller caps for higher speed requirements. (100nF, 1nF) If you ever look at a circuit that operates at GHz frequencies, don't be surprised if you see decoupling caps of 10pF or less.
-
Selecting decoupling capacitor values is one thing where practical experience really matters. In practice you usually just pick a value that sounds right for the frequency/application. In a nutshell the higher the frequency is the touchier it gets. One thing to watch out for is the caps resonating.
-
I think the "Go Real World", "Die Theory" posts have misinterpreted Dave's comment.
Dave pointed out that you usually guess (based on experience or by similar designs) or go with the manufacturers recommendations (which are usually available for devices with more difficult requirements) rather than calculating the value, which is true.
Any book on the topic will point out (around the same place they show the calculations) that it is impossible to completely model and calculate the required values because the exact requirements of the chip are generally unknown to anyone but the manufacturer and because an accurate model of your own power supply is also difficult to determine.
That doesn't mean you can get away with not knowing what is actually going on. If you've never seen the theory you may not even know which way to tweak things (bigger capacitors are always better, right..? ..!) or how to solve a problem you've run in to.
Also, I'm a technically a software engineer, and I hate working with programmers that don't own books (which would be most of them). There is plenty of room between a PhD and a cookbook/cookie cutter programmer, and the best programmers are somewhere in between.
-
If you want to learn about the actual values you'd need to use, or more about the subject in general
This is also a good reference from Analog Devices read section 7-3 pages 66 to 74 http://www.analog.com/library/analogDialogue/archives/39-05/Web_Ch7_final_J.pdf (http://www.analog.com/library/analogDialogue/archives/39-05/Web_Ch7_final_J.pdf)
-
quick noob question here: are these actually a different type of capacitor, or are they the same as others
but named decouplers because they happen to be used like that at the time?
-
quick noob question here: are these actually a different type of capacitor, or are they the same as others
but named decouplers because they happen to be used like that at the time?
Dave did a good video a while back about the various capacitor types. That would answer some of your questions. But these are just normal caps in a specialized use case.
Let's see... Episodes 33 part 1 (http://www.eevblog.com/2009/09/26/eevblog-33-1of2-capacitor-tutorial-electrolytic-tantalum-and-plastic-film/) and 33 part 2 (http://www.eevblog.com/2009/09/26/eevblog-33-2of2-capacitor-tutorial-ceramics-and-impedance/).
-
quick noob question here: are these actually a different type of capacitor, or are they the same as others
but named decouplers because they happen to be used like that at the time?
Some authors in EMC literature treat them as the same. The distinction is made on the basis of capacitance value and position in the circuit, but the theoretical treatment is the same.
Alex
-
ic thxz :)
-
I wonder why no ICs ever come with decoupling capacitors built in?
This would probably only be any good for high speed parts of course. Surely etching a 100pF capacitor onto the die near the power supply pins would help a lot, even if it still required a larger external capacitor. Another idea would be to encapsulate a small ceramic capacitor in the casing so it's nearer to the die. Built-in capacitors would also help to simplify PCB design as well as increase the operating speed.
-
I wonder why no ICs ever come with decoupling capacitors built in?
Everything is possible but as a general rule capacitors take up alot of die space since they tend to be physically large for any decent capacitance.
Years ago, they used to sell IC sockets for the standard DIP packages that had a 0.1uF cap across the standard pins, so you didnt need to remember to put down 0.1uF everytime you placed a logic chip.
http://www.conrad.com/IC-sockets-with-capacitor.htm?websale7=conrad-int&ci=SHOP_AREA_27787_0205025
-
It's not all like that of course, there are times when you need to accurately calculate values like this for some apps.
For higher frequency circuits and sometimes an audio circuit, I typically use a RC circuit to decouple, the circuit will look the same but with a series resistor added between stages and you'll be looking for a time constant based on the frequency you are trying to decouple. Generally you try to make the resistor as small as possible so you don't lose your voltage so some of the caps can be pretty large, it depends on the frequency really. But in this case I would advise you to calculate it. Otherwise as others have said you are simply moving around your circuit looking to short any AC on the DC rails to ground and any old low inpedance cap will do. At microwaves I'll use a sequence of caps of differing values in parallel since I am looking to shunt a wide range of frequencies to ground. The caps at a high enough frequency stop being caps, they have self resonances and many have nasty series resistances, so a spread of values helps you out here.
-
Apropos, I did a measurements using a spectrum analyzer (R&S FSV7) with a tracking generator a while ago about which bypass capacitor arrangement is best combination and arrived to a conclusion that it seems to be best to simply just put many as large-valued as possible capacitors in physically smallest package (smaller package = less inductance, thus higher resonant frequency) in parallel. This result agrees with one book I have about EMC, where the author arrived at same conclusion. For comparison, I also measured wide copper tape (any capacitor is likely not to be better than this, but clearly copper tape causes difficulties at DC) soldered/glued in place of the capacitor(s). It seems that the jig geometry is the limiting factor here. Narrow copper tape is copper tape just wide enough to bridge the cap. Setup is sensitive enough to distinguish if copper tape is soldered or just connected using a conducting glue.
If anyone has different results for real-world measurements using a realistic geometry, and not just theoretical idealized speculation, I'd like to see them. Different values gave parallel resonances which hampered the result, whereas paralleling same value reduced the impedance for whole spectrum (6 dB improvement on impedance when doubling amount of capacitors).
Thus, how the capacitors are connected (geometry), is at least as important than the capacitors themselves. As you can see, 4 paralleled 100n capacitors are better than equivalent amount of different valued capacitors, except for narrow frequency bands.
(http://koti.mbnet.fi/jahonen/Electronics/Measurements/BypassCaps/Bypass capacitors (ceramic+coppertape) Z.png)
Making a seemingly simple short circuit at high frequencies is very difficult. Even slightest inductance spoils the whole show. Here is the jig, set up with copper tape. Of course, when capacitors are measured, the copper tape is removed.
(http://koti.mbnet.fi/jahonen/Electronics/Measurements/BypassCaps/LRC-jig_with_coppertape.jpg)
Regards,
Janne
-
One way to look at it is this: you want the voltage supply *to the chip* to be the same no matter what. An interesting characteristic of CMOS logic is that it draws almost no power in steady state, but very fast chips like 74AC logic can draw an amp for a nanosecond while switching states. The large peak current means you need a low resistance to avoid a large voltage drop, and the fast rate-of-change of current means you need a low inductance. You need a charge storage device that can respond to very fast changes in load.
In very critical circuits you may need to have multiple decoupling capacitors -- for instance a 100 nF capacitor using a high-K dielectric can store a lot of charge, but is a bit slow to respond. You may need a 1-2 nF device in parallel with a low-k dielectric that has an extremely low series inductance and resistance.
Finally, you may have to worry about resonances between the bypass capacitors and the effective inductance of the PCB trace or the voltage regulator. If this happens, there can be a certain characteristic frequency at which there is a parallel LC resonance and corresponding high impedance. If the load current varies at near that frequency, there will be a large voltage drop on the LC circuit and the IC will see a large time-varying voltage. The usual way to handle this is to add a small (like an ohm) resistance into the supply line. Ideally this damps the high frequency resonance while not degrading the low frequency behavior unacceptable.
-
Just for idle amusement, I did an experiment a while ago - on a 2-layer board with FPGA running at 36MHz driving quite a lot of I/O, I took off all the decupling caps, leaving just a single 1u ceramic on the 1.8 and 3.3v regs and it still worked fine...
Not suggesting it for production though..
Nowadays my default decoupling caps are 0805 1u X7R ceramics, as costs is the same as 100n and eliminates the need for larger bulk decoupling. I only use 100n when space is tight.
-
Just for idle amusement, I did an experiment a while ago - on a 2-layer board with FPGA running at 36MHz driving quite a lot of I/O, I took off all the decupling caps, leaving just a single 1u ceramic on the 1.8 and 3.3v regs and it still worked fine...
Not suggesting it for production though..
Nowadays my default decoupling caps are 0805 1u X7R ceramics, as costs is the same as 100n and eliminates the need for larger bulk decoupling. I only use 100n when space is tight.
Something like that might still function correctly, but you probably had a lot of EMC emissions.
Neil
-
Hello all, sorry for bumping a very old (but always actual) topic.
First, thanks to jahonen. That is one of the most straightforward test I have ever seen on the "decade myth".
In book "PCB Design for Real-world EMI Control", by R. Archambault. ISBN 1-4020-7130-2 http://www.amazon.com/dp/1402071302 (http://www.amazon.com/dp/1402071302)
At chapter 8.4, there is 16 pages explaining a very similar experiment, but on a much larger scale: 15 SMA connectors and 60 capacitor locations.
The conclusions are the same: Take the largest value you can both afford and have space for, knowing that for the same value the smaller packages performs better.
Also, a tool from TDK shows the frequency response of their ceramic capacitors. Here is what I have plotted. Notice how package size impact the inductive right part, and the value iMpacts the capacitive left part. Also notice how little the "100pF" /they/ tell us to add with the 0.1uF does next to nothing below 750MHz.
(http://img20.imageshack.us/img20/2996/jw1.png)
Hope you enjoy this!
-
I wonder why no ICs ever come with decoupling capacitors built in?
Some FPGAs and processors come with decaps builts-in. Check e.g. Xilinx Virtex series.
-
It seems like a black art to me, especially on digital circuitry. I fully understand digital logic but what kind of mindset helps you look at digital devices also as analog devices?
Thanks for any insight you have,
- Fatlimey,.
There are (at least) two ways to look at a capacitor for decoupling: as storage for charge, and as a "impedance shunt". The first is for supplying charge to the capacitive load, the latter to shunt the inductive reactance on the collector/drain of the output transistor. [I refer to 'output' even though the driven node may be internal.]
First, simultaneous switching outputs is one parameter to consider. If you have a device driving a (large) capacitive load (say 32 bit address and 32 bit data with 50 pF on each output) you have 3.2 nF total load. In order to avoid a voltage drop of say 5% at the closest located (ideal) "decoupling" capacitor, you'll need 19x the load, i.e 64 nF. (capacitive voltage divider) However, the rise time of modern logic is so short so in practice you'll need plane capacitance to avoid local voltage drops due to the inductance between the decap and device. This also helps prevent EMI. For small devices and/or small Cloads, the plane capacitance naturally gets less important.
Note that this implies that the decap only is "active" for low-to-high transitions. For high-to-low transitions, a low inductance return path is needed to avoid ground bounce. The decap is not involved.
Secondly, the output stage might be seen as a open emitter/source stage. The gain is gmXC, and gmXD, respectively. The decap obviously keeps the gain down, which is what you want to avoid oscillations. This is just like any analog amplifier stage.
The reactance of the decap vias quickly dominates over the plane inductance, meaning that the location is not critical if you just consider a simple case (one driver, one load), assuming that the decap is directly coupled to power/gnd planes. However, the decaps must be placed so that transients currents doesn't disturbed other, more sensitive parts.
Altera has a spreadsheet for help on calculating the proper decoupling, usable for general purpose; not only for Altera devices. I can't find it now, but I count on help from the community :) The crux is to estimate the power on each supply. Worst case approach i.e. a transient current from zero to max may be needed to be on the safe side e.g for a processor that is in deep sleep and goes fully active.
"Poking around until the weirdness disappears?" is of course not a good idea. You don't want to encounter that type of problem...there are enough problems getting a system up and running, so you don't want random glitches making your system go wild. Imagine, you might have verified a system "fully" and everything is fine. Then you add a function, and suddenly it (sometimes) resets in elevated temperature. In that situation, you really want to be sure that it's NOT the decoupling that is the culprit. And then, if it is, you're still lucky that you found it so early! It could have been a field upgrade that made it crash, and make every customer buy the competitors product next time...
-
But the basic answer is that, in general, when it comes to decoupling capacitors we just pretty much pick the value out of the air.
That may be true for hobby stuff but it isn't true for real design.
We go so far as to actually run impedance plots on capacitors , find the correct mix to get a band in which the decoupling works.
I'm working on a biphase switcher right now. I just spent a whole day looking at the spectrum on the output , finding where the peaks are and finding capacitors that are in resonance a those frequencies to dampen the noise.
the board layout plays a role , the power grid plays a role , even the supply topology plays a role.
I am tweaking the input capacitors going into the switching regulator as well as the output bulk capacitors to get this thing to be as noise-free as possible.
For large boards the board is powered up under load and a network analyser makes a plot of the power rail spectrum. and then capacitor finding takes place. there is even special software where you feed capacitor models and it shows you to rejection impedance over frequency. you bet your ass that people making those tablets and cellphones are optimizing the snot out of it . even simple things like little wifi or Bluetooth modules are carefully tuned. you'd be creating so much crap in the spectrum the sensitivity would go to zilch..
on the harddisk front : the chip is actually designed with the real external capacitor models in account. don't you dare replace a 0805 tdk 22uf 6v3 x7r with a murata ... it will not work as well... it is really that specific.
-
Yes, we also "poke around until the weirdness/problem disappears"!
Sometimes literally... Many a time have I needed an extra little capacitance to make something work, and I simply poked a wet pinky at it...
Works a charm ;)
-
There are actually decoupling capacitors specially designed for GSM phones, where they have a low impedance point carefully controlled so as to fall at the centre of each of the GSM frequency bands, so it has a low at 800, 1800 and 2700MHz so it can decouple all 3 bands in a GSM chipset with a single component. TDK makes these, and I assume they are also avalable from other sources, though probably not as a hobby part.
-
There are actually decoupling capacitors specially designed for GSM phones, where they have a low impedance point carefully controlled so as to fall at the centre of each of the GSM frequency bands, so it has a low at 800, 1800 and 2700MHz so it can decouple all 3 bands in a GSM chipset with a single component. TDK makes these, and I assume they are also avalable from other sources, though probably not as a hobby part.
Maybe not quite the same thing, but you _can_ get microwave capacitors with a controlled Q and a known, sharp series resonance for delicate VHF/UHF hobby work. Just a question of knowing they exist, and not mind paying a lot more per capacitor.
-
I'm wondering about suppressing physical switch transients... Say, I have a switch that pulls a pin to ground when closed. Is there a way (and a point) to get rid of, or at least dampen the sawlike transients, and instead get a smooth voltage slope?
I'd appreciate if someone could point me to an example circuit if there is a best practice for this sort of thing. :)
-
RC filter?
-
It's common to throw a 0.1uF cap across the terminals for that reason.
-
That still gives you a sharp falling edge. I don't know why that's an issue, but if you really want both transitions smooth, I'd use a low pullup resistor (4.7k perhaps), then a separate RC filter with a much higher resistance (47k - 100k) to filter that voltage. That way R is close to equal on both edges (Rfilter on the falling edge, Rfilter + Rpullup on the rising edge).
-
Fun topic, Bruce Archambeault actually spoke at a IEEE EMC Conference that I was at a few years ago.
Also recommend Ott and I think Lee Hill of Silent Solutions does one of the best seminars.
Best part is that it "always depends" but I have seen certain situations where we were having EMI issues at a given frequency, started populating decoupling capacitors with a device that had a SRF in that same band and life was good.
I think that aside from doing power analysis like free electron describes the "deep V" method is most recommended and a general best practice from most of the speakers that I've heard.
Regardless of on package decoupling on something like a Xilinx FPGA, I would also put them at the board level.
Sent from my iPhone using Tapatalk 2
-
I'm more worried about the mini sawtooth / square wave that metallic terminals tend to cause. I'm pretty sure no IC likes that. A sharp drop or rise is okay I guess.
By the way I've been reading up on noise suppression filters lately, and it seems that nowadays it's all caps in low frequency range... :) I wonder if the reason chokes fell out is due to their size and weight.
-
I'm more worried about the mini sawtooth / square wave that metallic terminals tend to cause. I'm pretty sure no IC likes that. A sharp drop or rise is okay I guess.
Huh? Why? It's not inductive, you're not getting sharp spikes. Do you have a storage scope handy? Hook a button up to it and see what it captures - it's a lot gentler than you'd imagine.
I wonder if the reason chokes fell out is due to their size and weight.
Yup.
-
Another question. :)
Say I have an area of copper on the PCB that is totally surrounded by high impedance components... like the output of a voltage divider made up of two 1MOhm resistors, fed into the non-inverting input of an op-amp. I'm thinking that the amp may start amplifying a lot of EMI in this configuration - should I add a capacitor to ground?
Also, should the two power rails of an op-amp be connected with a capacitor, or is that only for digital ICs?
...and, what about the gate of various FETs? Usually the pulldown/pullup path is really high impedance, as we don't want to waste current there... Is there a risk of EMI turning the transistor on and off with, say, a 1MOhm pulldown to ground, and the positive signal turned off (let's assume infinite resistance)? Should there be a capacitor in parallel with the pulldown to give a lower impedance at higher freqs?
-
Say I have an area of copper on the PCB that is totally surrounded by high impedance components... like the output of a voltage divider made up of two 1MOhm resistors, fed into the non-inverting input of an op-amp. I'm thinking that the amp may start amplifying a lot of EMI in this configuration - should I add a capacitor to ground?
Use a guard trace. Buffer the signal to get a low-impedance version, then run that through a trace surrounding the high-impedance parts. No current will leak across zero potential difference. Ideally, you should unmask the trace so there is no leakage through the solder mask, but at a 500k Thevenin impedance you hardly need that except for very high-precision applications.
If you're concerned about high frequency EMI that could jump the guard you will need full shielding, but test first. The lily is pretty enough without a gold finish.
Also, should the two power rails of an op-amp be connected with a capacitor, or is that only for digital ICs?
I think it's a good idea. It's not as necessary, and a lot of low-precision, low-frequency analog circuits leave them out and just use one bulk capacitor per analog section. I tend to decouple everything as well as I can when practical - easier to throw a couple caps down than figure out later where I need them.
-
Also, should the two power rails of an op-amp be connected with a capacitor, or is that only for digital ICs?
Only in a single supply application (or in some special applications).
As a standard technique it is very good practice / highly recommended to decouple each opamp supply pin to ground, thus using two capacitors per opamp package in a dual supply configuration. The usually recommended size for audio is 0.1uF, with some larger 'bulk' capacitors, 10-100 uF or so, scattered about the board at regular intervals (5 cm radius or so).
High power, high frequency or other odd configuration opamps may need more/different decoupling than this, but this is usually specified in the datasheet.
You frequently see just one decoupling cap per opamp (package) used in circuits designed by beginners, connected rail-to-rail, but this is usually wrong. Analog Devices has several app note on this whole issue, explaining why this is so and that generally you need to use two caps, given how the current flows out of the opamp output.
...and, what about the gate of various FETs? Usually the pulldown/pullup path is really high impedance, as we don't want to waste current there... Is there a risk of EMI turning the transistor on and off with, say, a 1MOhm pulldown to ground, and the positive signal turned off (let's assume infinite resistance)? Should there be a capacitor in parallel with the pulldown to give a lower impedance at higher freqs?
Answer similar to the high impedance summing node for an opamp. If capacitance isn't an issue, then you may sometimes want a guard ring or added capacitance, but you need to test. Frequently this question is another reason why you should use a double sided PCB layout, one side being a solid ground fill below any critical, high frequency sensitive areas and components. The copper foil will act both as a small capacitor from any high impedance nodes to ground, and it will be an electrostatic screen, giving at least a partial screening against surrounding EM fields.
-
Thanks for the replies :) So a Thevenin resistance of 500k isn't that critical? That's somewhat of a relief. :)
Buffer the signal to get a low-impedance version, then run that through a trace surrounding the high-impedance parts.
As in, get the output of the op-amp and connect it up to the guard traces?
The usually recommended size for audio is 0.1uF, with some larger 'bulk' capacitors, 10-100 uF or so, scattered about the board at regular intervals (5 cm radius or so).
So in a single supply audio scenario, if I place a .1uF at the power pins of each op-amp, and a single 10uF electrolytic on the centre of the power rail (it's a small PCB), that should take care of most problems? Or do I need a 10uF per op-amp?
a double sided PCB layout, one side being a solid ground fill below any critical, high frequency sensitive areas and components
This sounds like a pretty cool thing to try. :D What about component pins? Does it cause problems if I have cutouts in the plane? (I'm doing through-hole now, for ease of assembly.) I've heard that holes in a plane can bring in unwanted inductance. Or is that only in multi-megahertz applications?
-
Yes, connect the output of the op amp to the guard trace, but only if it is at the same potential. If the op amp has (above unity) gain, I would connect the output of the feedback voltage divider to the trace instead (provided it has a much lower impedance than the high impedance input). If the op amp is inverting, I'd use a second op amp to get the guard trace potential.
So in a single supply audio scenario, if I place a .1uF at the power pins of each op-amp, and a single 10uF electrolytic on the centre of the power rail (it's a small PCB), that should take care of most problems? Or do I need a 10uF per op-amp?
Sounds fine. Remember that the capacitors should go to whichever rail current will return to - this means that if you have a bipolar power supply and the output current sinks to ground, you need two capacitors, each between a rail and ground, not just one between the rails.
Just one between the two rails could actually hurt your power supply rejection - if there is noise on just one rail, you will couple it onto the other as well.
I've heard that holes in a plane can bring in unwanted inductance. Or is that only in multi-megahertz applications?
Yup. Don't worry about it.
-
guys, the question you need to ask yourself first is
- what am i trying to do ?
there are 3 possible answers to that question
- trying to remove crosstalk in an analog system. like keeping the induced voltage ripple from a power stage out of the preamplifier
- making sure the switching induced voltage ripple on a digital rail doesn't cause my flipflops to go wonky ...
- solving an electromagentic compliance problem.
each problem has its own unique attack vector and strategy. and there may be additional criteria that can make this stuff very difficult.
Most difficult is the beancounters. don't add cost ! reduce the bom , reduce the number of to be placed parts as it reduces assembly cost. don't specify 5 different values if 4 will do ( economy of scale. buying 2 million 100 nf caps i cheaper than buying 1 million 100nf and 1 million 10nf )
a second difficult problem is : you only got this much room and it can only be that tall...(cellphones, tablets, smartphones, laptops ,diskdrives )
let's start without the additional criteria
analog domain : crest factors of signals are generally low and edges are slow. stuff that doesnt draw a lot of current doesnt need a lot of bypass cap. the caps are mainly used for local filtering of the power rail if you are far from the source on a daisy chain construction. if your analog power structer is a well coupled power/ground plane the decoupling caps don't do jack-shit. opamps have good psrr. loose transistor circuits will be powered via a lowpass filter ( 10 ohms folowed by a 10uf or 47uf ceramic to ground creating a clean local rail.
if you have fast edges you have peak currents. then you need local caps close to the power pins of the device driving these signals. these caps need to be tuned so they can release their energy fast enough. ceramic caps are so good these days that you wil get away with a couple of 100nf shunting the rails.
for really high frequencies the effect of the caps becomes negligible as you get far more dampening from the power planes in the board themselves (provided you have well coupled power distribution planes).
DANGER : local regulators do need good output decoupling as they can not take in energy ! the output impedance of a regulator delivering current is very low. good. the outpu impedance of a regulator tring to absorb energy is infinite
so , if you come from the power plane in to the pass element of the regulator, into your circuit you lost all the effect of the plane. you need to reconstruct it locally using caps. the mass effect is gone. if the local circuit drives anything reactive that may feed energy back into the rail you need ot be able to shunt that locally.
example : i have a plane with 15 volts on it. a local opamp needs 5 volt so i place a little 5 volt regulator close and make alittle power island. the opamp drives a reactive load ( coil , cap ) so energy can flow back into my local 5 volts rail , lifting it above 5 volts. voltage reglators are on-demand only. do i have 5 ? no -> add a bit electrons by sending the pass element in conduction. do i have 5 ? yes -> turn off the pass element. so if energy comes back and the 5 volt rail lifts above 5 volt the regulator just turns off the pass element ! at that point you are effectvely disconnected from the main bulk and plane decoupling before the regulator. o you will need something locally that can shunt this energy to ground.
digital domain:
edges are fast current peaks during switching especially in cmos. so you need to shunt the ripple locally by peppering one cap per chip. this used to be true in ttl and 40xx world...
complex chips have their own strategy.
As edge speed increases the capacitance need to be tuned. modern chips are all edge controlled , or differential (lvds , pcix,sata ) done to reduce ripple.
compliance:
this is the kick in the butt. while your system may work perfectly fine with 1 100nF cap it may fail the compliance testing miserably. standing waves created in the board , peaks in the spectrum .. loose plane edges forming a dipole antenna radiating in one direction... they may all be casue for failure. and that when the magic begins .... now you need to find the failing frequencies , the spot where it emanates from , find the exact value cap that is tuned on that frequency and shunt the energy. this is where emc chambers , network analysers , field solvers and all the other epxensive stuff comes into play. this is greybeard / wizard / deep pockets with big wads of cash territory.
and when you finally got it passing the beancounters and mechanical boys step in ..... wash -rinse- repeat ...