| Electronics > Beginners |
| Demodulation of a data |
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| fateme mrbs:
--- Quote from: mikerj on August 25, 2018, 12:11:27 pm --- --- Quote from: fateme mrbs on August 25, 2018, 10:13:55 am --- --- Quote from: mikerj on August 20, 2018, 04:51:14 pm ---. There will always be some latency between input and output. --- End quote --- the latency is not important. but the width of the pulse is. it should only cover the higher level pulses --- End quote --- Does each separate pulse represent one bit, or is one bit represented by many pulses (e.g. 8 pulses for a logic 1)? --- End quote --- the latter. one bit is represented by 8 pulses. [/quote] If the latter, if there always the exact same number of pulses and pulse timing for each bit? [/quote] almost, when i monitored it over a longer time. sometimes one pulse was missed. (7 pulses for a logic 1) |
| fateme mrbs:
--- Quote from: mikerj on August 20, 2018, 04:51:14 pm --- If the amplitude and timing of the pulses is well defined as shown i.e. the logic 1 pluses are always significantly higher amplitude than the logic 0 pluses then you may be able to feed the signal into a (very fast) comparator with a suitable threshold set (somewhere between logic o and logic 1 values), and use the output to trigger a (re-triggerable) monostable with a period just slightly longer then the period between your pulses. The downside of this would be noise immunity, and getting the 0/1 duty cycle correct --- End quote --- I have these pulses after the comparator. (first picture) I tried using a monostable without having those more widely spaced pulses, (they were supposed to represent a logic 'zero'). and the result is good. But when I use the same monostable WITH the more widely spaced pulses, the result is crazy! Why is that so? :( |
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