Electronics > Beginners
Derivation of stability criterion for type 3 digital PLL
(1/1)
promach:
Could anyone help to derive the following expression (4.23) which is the stability criterion for type 3 digital PLL ?

Note: Screenshots are taken from Floyd Gardner's book : Phaselock Techniques 3rd Edition



Navigation
Message Index
There was an error while thanking
Thanking...

Go to full version
Powered by SMFPacks Advanced Attachments Uploader Mod