Author Topic: Designing a digital input  (Read 983 times)

0 Members and 1 Guest are viewing this topic.

permal

• Regular Contributor
• Posts: 107
• Country:
Designing a digital input
« on: May 07, 2017, 05:48:43 pm »
This question is a continuation of my earlier question.

In an attempt to learn more about designing a digital input for both AC and DC, I've come up with the attached schematic. My intention is to make the input active high and have shorter rise and fall times compared to those seen in the schematic in the linked question. The input in questions will be connected to an ESP32.

As per the previous question, the purpose of the polarized capacitor is to even out the on/off switching of U1 when AC is applied.

I'm wondering if this is a viable way to design an input? The rise and fall times becomes rather long (11ms rise/47ms fall to reach required voltage levels) when I try to limit the current draw while the input is active. I'm concerned that during the time the voltage level is between what is considered low and high might cause erroneous reading on the uC. Of course, the fall time mustn't become shorter than the fall/rise of the applied AC for it to have any actual effect so it all must be balanced out.

Would it be possible to reduce the rise/fall times to the uC by the use of an opamp? I know very little of them, but I seem to remember that they can be used to create a nice looking square wave from an analog signal?

Thank you!
« Last Edit: May 07, 2017, 06:29:56 pm by permal »

• Super Contributor
• Posts: 1875
• Country:
• Reactor Operator SSN-583, Retired EE
Re: Designing a digital input
« Reply #1 on: May 08, 2017, 01:13:23 am »
If you look at datasheet test ckt for Tr and Tf it grounds the emitter,
places R in collector, takes output at collector. For 100 ohms results
seems to be 5 uS for either transition. This would also eliminate need
for electrolytic. Electrolytic is giving you the very slow rise and fall times.

Note this configuration logically inverts vs yours is non inverting.

Regards,
« Last Edit: May 08, 2017, 01:15:21 am by danadak »
Love Cypress PSOC, ATTiny, Bit Slice, OpAmps, Oscilloscopes, and Analog Gurus like Pease, Miller, Widlar, Dobkin, obsessed with being an engineer

permal

• Regular Contributor
• Posts: 107
• Country:
Re: Designing a digital input
« Reply #2 on: May 08, 2017, 05:39:15 pm »
Note this configuration logically inverts vs yours is non inverting.

Perhaps I wasn't clear in my initial post, but that is the very thing I want to avoid for this thought experiment.

Is it possible to have a non-inverting input with acceptable rise/fall times towards the uC? If so, how?
« Last Edit: May 08, 2017, 05:56:11 pm by permal »

• Super Contributor
• Posts: 1875
• Country:
• Reactor Operator SSN-583, Retired EE
Re: Designing a digital input
« Reply #3 on: May 08, 2017, 10:37:36 pm »
One alternative is to config UC inputs as Schmidt, essentially eliminating
any concern for rise/fall time. Or use a comparator with hysteresis.

Regards, Dana.
« Last Edit: May 08, 2017, 10:51:49 pm by danadak »
Love Cypress PSOC, ATTiny, Bit Slice, OpAmps, Oscilloscopes, and Analog Gurus like Pease, Miller, Widlar, Dobkin, obsessed with being an engineer

The following users thanked this post: permal

Smf