Hello, I need to design a set of voltage references for a 16-bit DSM. The two most constrained go to the input DAC of the DSM so all the noise on these is coupled directly to the input. The accuracy is not as important but the higher the better. The specs would be the following:
- Low noise: < 20 nV/sqrt(Hz)
- Nominal value of 0.4V and 1.4V, but better if they are adjustable. I have a common mode of 0.9V which should be in the center, I don't know if I can make use of this to generate a symmetric range.
- The current drawn by the DSM is a high frequency (i.e. 12.8MHz) pulsing current. The average is quite low however (way smaller than 1mA). To reduce the switching noise I want to use big decoupling capacitors at the DSM input pins (1uF or 10uF the biggest and then a ladder of decades (e.g. 10u-0.1u-1n)
So far this is what I have tried and looked at:
- First I tried using the circuit in fig1 (some component references are different) to use my common mode to generate a symmetric signal using only one low-noise regulator. However I had stability problems with the opamp due to the big decoupling capacitors. What I did is add an emitter follower after the opamp and the feed it back to the negative pin. This solved the stability but the output voltage when the DSM was running was very noisy due to switching currents. The output measurements weren't very good either.
- I also tried generating both voltage references separately using the typical scheme seen in integrated voltage references (LDO-voltage divider+filter-opamp buffer stage) (fig2). I repeated the emitter follower stage after the opamp to decouple the opamp output from all the DSM capacitors. I think this kind of worked since the measurements were limited by a different issue but I still saw ugly switching noise on the oscilloscope. I can't confirm this is due to current fluctuations, but I don't think is due to PCB couplings. I was careful separating the digital and analog domains and using different regulators for both analog and digital pins. Advice is welcome nonetheless.
- I think the easier would be that the output voltage was the output of a LDO regulator to avoid using an opamps so I don't have to worry about stability, etc. The problem is there are no adjustable nor fixed regulators that can provide such low voltages as the 0.4V I need. I also looked at voltage references since the buffer is already integrated but from what I've seen they are fixed, the noise is quite high (at least the ones I've seen) and the voltages are not as low as 0.4V anyway
So I'd like to ask any of you with experience in high-resolution ADC measurements how to properly generate the bias voltages since I have a couple attempts and I'm still not convinced on the right way to do it. If you need any information about the components I used in the designs I will post it.
Thank you in advance.
p.d. the transistor in fig2 should be a NMOS