Morning all.

I've been playing around with JFETs in TINA TI in order to refresh my memory and managed to build this amplifier circuit (file see attached-schematic below):

and obtain the bode plot as shown below:

As you can see (ignoring the hump in the roll off at about 1kHz)) I get about 19dB gain between 10kHz and 1MHz, which is what I was aiming for (some gain between 10kHz & 1MHz)

The problem I have is that Id = 6.68mA, Vgs = -1V & Vds = 5.52V and From looking at figure 3 on the datasheet(

http://www.farnell.com/datasheets/2172091.pdf?_ga=1.96281884.1080831287.1470060388), that these values do not appear to match any of the curves on that table?

I'm quite confused as I was hoping to prove this correct. Have I done something daft? or even misunderstood something?

The method I used to calculate these values was to set the Vgs Bias to half the pinchoff voltage and set R1 using the approximation that Vgs=Id*Rs and equating Id=Ids=Idss(1-(Vgs/Vp))

^{2} - Schokly's Equation

Then, with a supply voltage of 12V I ideally wanted Vd = 6V and calculated R2 using ohms law.

C3 was adjusted till the desired roll off was acquired.

Another question: I realise the method I've described above doesn't really allow you to design the amp to a specific gain. Is there a correct way to design with a specific gain? Also id the maximum gain dictated by the JFET's maximum transconductance?

cheers for any advice and help