Crystal not oscillating (input to 74HC4060)

[Macka]

Hi guys,

I've got a bit of an issue with a crystal (actually 2 crystals) not oscillating (can't see the sine wave on my DSO and there's no output at the test points).

The crystals are connected to independent 74HC4060 14-stage binary ripple counters (http://www.nxp.com/documents/data_sheet/74HC_HCT4060.pdf) in the same configuration and same component values shown in the attached images.

This circuit has been known to work for others and is used in the Open.Theremin.Uno project; having said that, looking at the data sheet R18 (Rbias) is much higher than the recommended figure of 100k-4.7M Ohm. I have tested a 100kOhm in parallel with the with the 4.7M with no change.

I have my DSO in 10X mode and can easily see the oscillations of a 12MHz crystal on a microcontroller.

Note: all components are SMD

Data sheets for the crystals: http://www.ecsxtal.com/store/pdf/csm-7x.pdf


What should I be looking at/testing to sort this issue out?

Thanks

[edavid]

The 2.2K resistor value is too high.  You could probably make it 0 ohms.

[Andy Watson]

The 2.2K resistor value is too high.  You could probably make it 0 ohms.

Agreed. Also, at 7-8MHz, C17 and C18 could probably be reduced - try 20pF. And remember that if you probe the crystal directly with scope probe you will be adding 10M and ~10pF to ground.

Does the 4060 have sufficient and close-by decoupling?

[dannyf]

For that high of a frequency, putting a crystal is all it takes.

You may increase the feedback resistor. You may also use a serial resistor, either on the output or the input, to isolate the circuit resonation from the clamping diodes. Try 100k first.

[danadak]

R19 has various functions, in some cases limiting xtal excitation, others moving
phase to correct slope of xtal response. Also killing harmonic operation of the
xtal fundamental.

This might help -

http://www.ti.com/lit/an/szza043/szza043.pdf

http://www.rakon.com/component/docman/doc_download/223-ic-crystal-oscillator-circuits?Itemid=

Regards, Dana.

[Macka]

Lots of responses, thanks guys!

Ok, so I have bridged across R19 and R21 with a 330ohm resistor, the 8MHz crystal is now running perfectly and I'm getting 500kHz on the output Q4 (div by 16 output); I'll desolder the 2.2k from  R21 and replace with 220 ohms.

I'm still having issues with the 7.32MHz crystal, but I'll play with it some more. Still need to read the documents danadak posted.

[ElektroQuark]

Try lowering R18 to 1MOhm

[edavid]

Try lowering R18 to 1MOhm

Why do you think that would make any difference?

[ebclr]

[Zero999]

The lowest output frequency the 4060 can get from a 32,768Hz crystal is 2Hz, as it's a 14 stage counter. To get 1Hz, a 15 stage counter is required.

[danadak]

The R used to bring the cmos gate into its linear region is a compromise of
xtal loading vs generating offsets due to leakage.

The 74HC4060 spec has a leakage of + or - 1 uA, so that means the gate
will be offset by as much as Rfdb x 1 uA = 15 V which implies gate would be
at supply rails. Typical is .1 uA, or 1.5V for 15M fdbk.


Regards, Dana.

[edavid]

The 74HC4060 spec has a leakage of + or - 1 uA, so that means the gate
will be offset by as much as Rfdb x 1 uA = 15 V which implies gate would be
at supply rails. Typical is .1 uA, or 1.5V for 15M fdbk.

I think you are are reading the datasheet wrong... 74HC specifies 0.1uA max at 25C, with no typical value.  Actual input leakage should be below 1nA.

(See Figure 8 in this document: http://www.home.hs-karlsruhe.de/~bebe0001/74LSXX/74HCTxx.pdf)

You might want to consider the worst case current for a production design, but that has nothing to do with OP's problems.

[pelule]

I may have overseen, I am missing a potentially design critical information.
What is your the supply voltage (VCC)?
Most samples application for CMOS are based related to VCC >5V normally.
At lower voltage the circuit requires to be adopted as CMOS becomes slower.

[Macka]

I may have overseen, I am missing a potentially design critical information.
What is your the supply voltage (VCC)?
Most samples application for CMOS are based related to VCC >5V normally.
At lower voltage the circuit requires to be adopted as CMOS becomes slower.

Supply voltage is 3.3V; there is a 100nF cap across the supply within a few mm of the IC. PCB layout attached. If it's a voltage issue, other than increasing the voltage, what else can be done? Also why does the 8MHz work but not the 7.32MHz?

I've got some caps on order so I can try 10, 15 and 20 pF

Edit - just tested 18 pF caps, 4.7 MOhm R18 and 220 Ohm R19 - no luck

[Macka]

Try lowering R18 to 1MOhm

Was the first thing I tried. Also tried it in combo with R19 at 330 Ohm. I think the only other thing I can try is to reduce the caps on the crystal

[danadak]

From the NXP datasheet, attached, leakage specs.


Regards, Dana.

[Macka]

R19 has various functions, in some cases limiting xtal excitation, others moving
phase to correct slope of xtal response. Also killing harmonic operation of the
xtal fundamental.

This might help -

http://www.ti.com/lit/an/szza043/szza043.pdf

http://www.rakon.com/component/docman/doc_download/223-ic-crystal-oscillator-circuits?Itemid=

Regards, Dana.

Ok, so going through the crystal data sheet:
C0 = 7pF
CL = 18pF (part number) or 20 pF (typ)
ESR = 60 Ohm
Drive level = 500uW

From the counter data sheet:
CI = 3.5 pF (Input capacitance - is this gate input capacitance?)

From the second link:
CL = C1 + CI
C1 = 18 -3.5 - 14.5 pF

For increased gain C1 < C2, so I could potentially use C1 = 15 pF and C2 = 33 pF? (the example does not explain the selection of C2)

From figure 5, I need minimum 50 Ohm to keep the drive below 500uW, I have 220Ohm, so 50uW dissipation, perhaps not enough current getting to the crystal, though it worked fine for the 8 MHz one
Figure 5 only applies for the design given as the example (not sure how to calculate the curve for my values)

Like the example, the gate is inverting, so phase shift = 180°
Phase Shift (propagation delay) = Propagation Delay * Working Frequency * 360° =  Propagation Delay * 7.3728MHz * 360° = Propagation Delay * 2654208000 = ??
Phase Shift (working frequency) = arctan(Fosc / F3dB) = arctan(7.3728MHz/F3dB) = ??

So I have a few unknowns, I don't really know how close they have to be to 360°; the example comes to  354°

[edavid]

Try lowering R18 to 1MOhm

Was the first thing I tried. Also tried it in combo with R19 at 330 Ohm. I think the only other thing I can try is to reduce the caps on the crystal

Did you try making R19 zero ohms?  Did you try a different crystal?

From the NXP datasheet, attached, leakage specs.

Yes, just as I said, there is no typical value specified.  If you refer to the document I linked, the normal value is below 1nA (see graph below).   In reality, only a damaged part will have 100nA leakage.  This is certainly not what caused the OP's problem.

[danadak]

Leakage.

Good practice does not design to typical values. Unless one wants the oscillator to
"typically" start, but not always.

Unless I missed it we do not know if the gate was in linear region with the 15M,
one has to measure output to see if it is biased up properly.

There are a number of leakage mechanisms involved on a cmos input, from the
fet itself to the protection networks employed to make the part robust. Process
and surface states of the silicon enter into the picture.


Regards, Dana.

[edavid]

Unless I missed it we do not know if the gate was in linear region with the 15M,
one has to measure output to see if it is biased up properly.

Yes, you missed it.  When he changed the series resistor, the 8MHz oscillator started working.  Therefore, the problem was not the biasing resistor.

There are a number of leakage mechanisms involved on a cmos input, from the
fet itself to the protection networks employed to make the part robust. Process
and surface states of the silicon enter into the picture.

True, but not relevant, since all we care about is the total.

[danadak]

Yes, you missed it.  When he changed the series resistor, the 8MHz oscillator started working.  Therefore, the problem was not the biasing resistor.

Actually no, the G thru the device N and P MOS transistors not the same, so if biasing is offset
so is behavior. Further the bias R and input C contribute to loop dynamics. So fact that one
component change made osc startup does not alleviate proper design for the rest of circuit.
Oscillation is not a guarantee of proper bias point.

The point about where leakage comes from stands as is. Informational.

More information -

http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee141_f01/Notes/chapter5.pdf

http://webpages.eng.wayne.edu/cadence/ECE6570/doc/lect6_1.pdf

Regards, Dana.

[pelule]

I guess we all may agree to following points:
+ the CMOS IC is designed for crystal use, even at 3v3 according to NXP spec
+ it works with the 8 MHz crystal (at least badly/sometimes) -> the IC is at least not fully damaged
+ it does not work with the 7.3728 MHz crystal (data is available)
-----------
My 1 step of analyis:
+ in principle it is a feedback (looped) amplifier
+ a good designed oscillator is a badly compensated feedback amplifier, it thus start to oscillates
   (at amplification you don't want it, in this case it is required, you need it)
1st conclusion = it does not start (or stops again) the oscillation, because the compensation is wrong (in our case: too much damping)

My 2nd step of analyis:
+ too much damping means a too low ac load - a too low resistance at the target frequency of 7.3728 MHz
+ the damping circuit is build out of the crystal (a band path at target frequency), the series & feedback resistor and the clamping capacitors.
+ it ~works at 8 MHz, but does not at 7.3728 MHz (frequencies are very close to each other) with the same rest of parts in the compensation
2nd conclusion = the ac specs of the both crystal must be significant different
(I couldn't find an info, if the data sheet is for both crystals, but I don't believe)

MY SOLUTION
= either increase the amplification (reduce the effect of the damping)
--> reduce the parallel resistor (typicall one starts with 10 MOHm for CMOS, here we have 3V3, thus I would start with 1 MOhm)

= or reduce AC load (increase the ac resistance) of the damping circuit
--> you may reduce the resistor in line with the crystal (or directly start with zero Ohm)
--> you may reduce the clamping capacitors/increase there impedance (or start by leaving them away)

You may also calculate the optimum AC load using the equivalent circuit of the crystals and taking the values out of the data sheet

Does the comunity agee to my analysis/conclusion/steps to solution?

[Kalvin]

Could the 7.3728 MHz crystals be broken?

[pelule]

Could the 7.3728 MHz crystals be broken?

Yes, that would also explain the symtoms.

[Macka]

I haven't had any time (or parts) to work on this again until today.

After much messing about and hair pulling, I think I finally found the problem - seems there was a dry joint on the +ve rail  .

Definitely needed to reduce the series resistor (2.2k down to 220 Ohm), not sure about the parallel resistor (at the moment I have 5kOhm, down from 4.7M). Also, I swapped the crystal out for a 20MHz, now I have to swap it back and hope I haven't ruined it, since a replacement is potentially a few weeks away (stock levels and remote living). The 20 MHz crystal doesn't start without some capacitance, seems the probe on the series resistance side is sufficient.

More experimenting to find a better parallel resistor and cap combo to come.