Buck Converter (TPS561208) magic smoke

[Verbose1366]

Hey all. I recently got into PCB design and so I've been learning the ropes. I'm converting 12v to 4.5v to feed into an LDO.

I populated two PCBs with only the buck converter circuitry -- input and output caps, voltage select resistors, and inductor, leaving the LDO IC unpopulated. Both times, the TPS561208 puffed up in magic smoke and shorted VIN to GND. I fed in 12.5v from my benchtop power supply, which is well within the 17v limit on this buck converter.

I know my PCB layout isn't ideal. Looking at the datasheet https://www.ti.com/lit/ds/symlink/tps561208.pdf more closely, I shouldn't pass leads from VBST output, to R10, underneath the buck converter, but I still don't see why this would cause magic smoke and short VCC to GND. Even in that case, it may just cause the chip to work unexpectedly at times.

My question is, if if there's no resistive load present on buck converter output, could that cause the buck converter to short out internally? I would test it out, but I only have 1 buck converter component left, and wanted to check if there was some obvious oversight on my part before I did that

[pcprogrammer]

What kind of coil are you using?

L1 on the PCB seems a bit small to be a proper coil for a buck converter. Looks more like a ferrite bead foot print.

[xvr]

I know my PCB layout isn't ideal.

I'd rather say it's terrible. You have placed all the sensitive components as incorrectly as possible.

[mk_]

I know my PCB layout isn't ideal.

Well... not ideal as a descrition for as bad as possible... 
there is a whole side of Layoutguidelines in the datasheet - and believe me - these guidelines are not written just for fun.

[thm_w]

Lets see a photo of the built up board.
As pcprogrammer says, L1 looks way too small.

BTW when you power up your board, set current limit to some reasonably low level, maybe 50-200mA. Then hopefully if it shorts out nothing blows up.

[Verbose1366]

What kind of coil are you using?

L1 on the PCB seems a bit small to be a proper coil for a buck converter. Looks more like a ferrite bead foot print.

Yeah I went with a ferrite bead rather than a drum core. I matched the Henry value that I generated on Webench, thinking it would work, but just realized it suggested a drum core.

I wonder if that's my problem then. Either way, I need to redesign my circuit and actually follow the PCB layout the datasheet suggests

[tszaboo]

Ferrite beads are used to dissipate noise. Inductors to store energy.
Use TIs webench calculator to select components and do not deviate from the suggested parts. You have a lot to learn, but take this as a lesson, not as a failure.

[Verbose1366]

I didn't realize how particular buck converters were until I started reading into the datasheet more.

Thank you for a helpful explanation! There is definitely lots to learn

[Verbose1366]

Well, after reading the datasheet layout, I finally came up with a revamped buck converter layout. I laid out the parts in the recommended fashion, used VOUT/GND/VIN planes, more vias, and kept the feedback loop outside of the switching circuit. If there's anything obviously wrong with this one, I'm all ears. Thanks again for all the help!

[tszaboo]

You want more/bigger capacitors. For higher voltages the capacitor looses it's effective capacitance. It all depends on the goal, how much voltage ripple you want. But since you place an LDO after the switcher, you probably want as little as possible.
Otherwise it's not a bad effort. See if you can keep the switching node on one side (the track between the inductor and the IC).

[Verbose1366]

You want more/bigger capacitors. For higher voltages the capacitor looses it's effective capacitance. It all depends on the goal, how much voltage ripple you want. But since you place an LDO after the switcher, you probably want as little as possible.
Otherwise it's not a bad effort. See if you can keep the switching node on one side (the track between the inductor and the IC).

That's great info! I ended up doubling the input decoupling caps and output caps on the buck converter and increasing the size of them up to SMD 1206s, which actually allows me to run the SW node underneath between the inductor and IC -- effectively keeping the SW node on the same side of the PCB. I tried to connect C6 to the same side of the PCB as well, but I couldn't do that without breaking the ground pour node. So there's a trace running on the bottom layer of the board. Hopefully this actually fixed the things you suggested

[ Specified attachment is not available ]

[T3sl4co1l]

When you powered it on, did you set the source to zero then enable it, or did you set it to 12V and hot-plug the regulator?

Very common issue: https://electronics.stackexchange.com/questions/713381/correct-placement-of-series-ferrite-beads-to-avoid-dc-disconnect-during-power-cy/713473#713473

Tim

[Verbose1366]

When you powered it on, did you set the source to zero then enable it, or did you set it to 12V and hot-plug the regulator?

Very common issue: https://electronics.stackexchange.com/questions/713381/correct-placement-of-series-ferrite-beads-to-avoid-dc-disconnect-during-power-cy/713473#713473

Tim

I did not. I had no idea about DC bias in ceramic capacitors. It looks like adding an electrolytic capacitor, or higher rated ceramic caps, and possibly a TVS on the input would be helpful here. I'll run some simulations with LTSpice to see what it looks like.

Thanks for the pointer!

[Faranight]

Ceramic caps (MLCC) serve to reduce the current ripple while the electrolytics are typically used to manage the transient response for when there is a sudden change of load current. You need to use higher-rated ceramics to reduce the DC bias effect - use X5R or X7R caps rated for 25V or better yet 50V. You also lack a decoupling cap on the input - you typically put a 0.1uF MLCC in parallel to the input caps and put it as close as possible between the Vin and GND pins of the IC. Also, looking at the datasheet, that suggested layout on page 19 seems a bit sketchy to me.

Personally I would try to route the ground underneath the IC, connect it to the bottom layer ground plane through vias and put the input caps on the "south" side of the IC. This would free up the space, so you can put the inductor close to the SW pin (remember, the SW node is the noisiest node, so you want to make this area as small as possible. You also want to use a bit larger traces for the power path - I see you've already made them larger in your subsequent design, and it really doesn't hurt to use copper fills instead of traces. The feedback trace (and the resistor divider) should ideally be placed well away from the inductor to avoid noise being coupled into the trace. Placement of the output capacitors isn't that critical, but do place them somewhere close to the inductor output, and the ground can be connected to the bottom copper plane (assuming you have one - you should) by vias.

[T3sl4co1l]

Ceramic caps (MLCC) serve to reduce the current ripple while the electrolytics are typically used to manage the transient response for when there is a sudden change of load current. You need to use higher-rated ceramics to reduce the DC bias effect - use X5R or X7R caps rated for 25V or better yet 50V.

C(V) curve has no relation to rated voltage -- voltage is simply what it's guaranteed to withstand without failure.

Chip size has more bearing, but still is no guarantee they didn't simply fill that chip with empty dielectric rather than active area (electrodes).

Tim

[shapirus]

C(V) curve has no relation to rated voltage -- voltage is simply what it's guaranteed to withstand without failure.

It actually does depend on the rated voltage, at least sometimes. For example, here's what we can see in a datasheet, in this case for the Samsung CL series MLCCs.

Note how different the X7R 50V and X7R 16V curves are.




Another example, obtained from the Murata simsurfing tool. Two 1μF X7R capacitors, one rated 16V, another 50V:

[Verbose1366]

Ok I think I'm at a design I'm happy with. It's been a good week learning about buck converter PCB layouts. It really opened my eyes at how schematics may be correct, the layout can still wreck it.

Here's my (hopefully) final layout -- hopefully not messing something up in process. I already sent off my last design to be fab'd, but if I have to send off a new design, I'll have it made with the new design. It was only $4 for 5 boards, so it's not a big deal.

[T3sl4co1l]

It actually does depend on the rated voltage, at least sometimes. For example, here's what we can see in a datasheet, in this case for the Samsung CL series MLCCs.

Note how different the X7R 50V and X7R 16V curves are.

This isn't a characteristic sheet -- it's a series catalog, not particular part data; the curves would've been measured for random parts, and the figure is shown only for example.  At least, that's my best interpretation of the document.

They provide data (or, at least on some parts..) on their part database search, e.g.
https://weblib.samsungsem.com/mlcc/mlcc-ec-data-sheet.do?partNumber=CL32Y106KCVZNW
Otherwise-identical seeming parts often differ by 20% capacitance, at voltage, so it's worth checking.

Most often, one part has lower height, so is probably the same internal construction but less of it (fewer, thinner layers), but both rated for 50V or whatever.

Another example, obtained from the Murata simsurfing tool. Two 1μF X7R capacitors, one rated 16V, another 50V:

GRM21BR71C105KA01 and GRM21BR71C105KA01 are a much better comparison: they have the same outer dimensions including height, and one is AEC qualified but I don't think that really means anything to construction.  Whether they differ because of electrode arrangement or chemical composition, who knows; in any case, one example does not, a statistical study, make; inverse correlations also exist.

Tim

[Faranight]

Verbose1366: Any particular reasons you persist using the board traces with weird angles? Not that it's electrically wrong, it just hurts my eyes watching the design. You would typically use horizontal, vertical and 45°-angled traces only. Personally I would replace all the traces on the power path with copper fill zones. The U3 could use a GND copper fill underneath it that connects pins 2 and 4 together with some vias right underneath the IC - I'm not sure how much current you're planning to draw, but you would want to use multiple vias when connecting power paths to different board layers - this also helps with heat dissipation, and you can expect regulators to heat up.

I'm also not a fan of having U2's GND pin (pin 1) connected by only a single via to the bottom layer. Personally I would give priority to the power path and route the GND on the same plane right underneath the IC directly down to the 0.1uF decoupling cap GND terminal (you'd have to move C7 a little to the left). Then use multiple GND vias on the copper fill to connect it to the bottom plane, and you should probably include the C10 GND terminal in the fill (assuming C7 is the 0.1uF decoupling cap, and C10 is one of the regular input caps). I would only try routing the EN trace afterwards. The R10 and R11 are now well placed, far away from the noisy inductor, but I would modify the feedback trace somewhat, so that it samples the output voltage directly from one of the buck output caps, not from the inductor itself (you may have to re-arrange the caps a little i.e. put them above L1?).

T3sl4co1l: Yes, you are correct about the C(V) curve, but I generally found that MLCC caps with higher voltage rating typically have flatter DC-bias curves. You're also right about the package size - I forgot to mention that one.

[shapirus]

GRM21BR71C105KA01 and GRM21BR71C105KA01 are a much better comparison: they have the same outer dimensions including height, and one is AEC qualified but I don't think that really means anything to construction.  Whether they differ because of electrode arrangement or chemical composition, who knows; in any case, one example does not, a statistical study, make; inverse correlations also exist.

Well, I did not try to hand-pick them specifically to demonstrate the difference, I just looked up two caps with a significantly different voltage rating, but having the same dielectric type, capacitance, and SMD footprint with as many matching letters in the model number as possible.

Of course one example is not enough for statistics, but it is enough to disprove a generalized statement. My point is that this topic isn't as straightforward as it seems. In at least some cases rated voltage is not just about the safe operation voltage limit, but in other cases the capacitance vs DC bias curves do indeed match for caps rated for different voltages.

Now, what are other variables that can affect this? I think I may have found one. The simsurfing tool has a parameter called "T size(max.)[mm]", which I believe means physical thickness. And that seems to be the key: I compared several pairs that in one case had the same capacitance, SMD footprint size, thickness, but different rated voltage, and another several pairs that differed in thickness too. Guess what, in the first case their curves matched, in the second case they didn't: the thinner caps had their capacitance dropping more quickly.

[tszaboo]

Ok I think I'm at a design I'm happy with. It's been a good week learning about buck converter PCB layouts. It really opened my eyes at how schematics may be correct, the layout can still wreck it.

Here's my (hopefully) final layout -- hopefully not messing something up in process. I already sent off my last design to be fab'd, but if I have to send off a new design, I'll have it made with the new design. It was only $4 for 5 boards, so it's not a big deal.

(Attachment Link)
(Attachment Link)

The trace for your feedback resistors should come from the output capacitors, not the inductor. Otherwise it's quite OK, if you have a GND plane below this.

[T3sl4co1l]

Of course one example is not enough for statistics, but it is enough to disprove a generalized statement. My point is that this topic isn't as straightforward as it seems. In at least some cases rated voltage is not just about the safe operation voltage limit, but in other cases the capacitance vs DC bias curves do indeed match for caps rated for different voltages.

Exactly what I said was, "no relation" -- none at all, might be a matter of perspective...or hyperbole; but from a statistical point: it might be one way, it might be the other; there's no conclusion to draw here, or at least nothing strong.

Tim