I am not convinced that is what is being shown. There are two parasitic diodes from the substrate to the source and drain forming a parasitic bipolar transistor. The vertical MOSFET structure shorts out the parasitic base-emitter junction for all kinds of good reasons (1) but leaves the base-collector junction which forms the body diode.
Yeah, it's not too relevant anymore, literally speaking, since the reign of lateral DMOS passed decades ago. It would be more accurate moved around a bit, but reinterpreting the classic symbol for modern structures is perfectly fine in my book.
The symbol showing one diode seems to show the largely irrelevant (2) shorted base-emitter junction and I prefer the two diode symbol to make the base-collector junction explicit. In the past, that little substrate diode reminded me to watch out for operating conditions.
I don't like the diode, because it implies it's external. An IGBT co-pack is truly external, and the symbol reflects this.
Not that the rest of the IGBT symbol really means anything, either, sadly; the "insulated gate BJT" one is maybe more accurate, but less distinctive, and probably a bit disingenuous of an oversimplification, anyway.
(1) SCRs do the same thing with extra metalization for the same reason which is left off in sensitive gate SCRs.
(2) Vertical MOSFETs have gotten better but that parasitic NPN did not used to be irrelevant; you had to watch the operating conditions to prevent activating it and destroying the device. Is it ever a concern anymore?
I think so -- avalanche breakdown is still very much a concern, and it activates the parasitic BJT. While MOSFETs are typically rated for near-die-cracking discharges*, it's a one-time thing, and relying on it outside of the rated range (under repetitive use or at excessive peak current) is destructive.
*That is, Tj(max) limited. Please don't actually try to thermal shock your transistors...
A good example is a switching converter with excess stray inductance (unclamped), which causes repetitive avalanche, at whatever the peak switching current is. The voltage after avalanche is not nearly zero (as it is in the datasheet test case), but the full supply voltage, maybe 50 to 80% of rated Vdss (depending on how tight the converter design is being pushed..). The current tail after avalanche decays slowly, dissipating tons more energy than E(inductor) implies. (If nothing else, the inductor's energy adds with the supply anyway, so that E(diss) > E(inductor) to begin with.)
I don't actually know how fast avalanche charge clears; it's not like a full t_rr. Is it proportional to reverse-bias voltage? So if the body diode clears in, say, 800ns at 0.5V, is it 0.8ns at 500V? That would be fast enough not to worry. Purpose-made zener diodes tend to respond very quickly indeed (only a very small amount of excess discharge, visible at very low bias, where the noise voltage looks like a random sawtooth), but I don't have a feel for how much worse MOSFETs are in this mode of operation. (Proper BJTs are quite awful, but that's a side-effect of the 3-layer structure; I don't know of any diodes that avalanche in the same way. Possibly a very hard avalanche would activate the 3-layer structure in MOSFETs, but that would be difficult to achieve without destroying it somehow anyway, I suspect.)
Tim