Discreet startup delay?

[spec]

Capacitor between Q3gs improves dv/dt rating and slows down switching (better emi), think it is not really a concern in this application, but with this high impedance at the gate, me would feel better.

There is already a fair amount of capacitance at the gate as stated.

Slow switching would be a problem if you get out of the soa, NDP6020P is capable of DC operation with at least 1A@Vdsmax with appropriate heatsink 

You're raising a flag and saluting it. The main reason for a fast switch-on is to get the PMOSFET through the linear region fast to avoid potential oscillations: nothing to do with SOA or TJmax. With an application like this you have no idea what will be connected to the drain of the PMOSFET- could be inductive, capacitive, negative resistance or a combination of all of these and others.

VGSmax of 20V or greater, still with a VGth of 1V or less - would claim it near impossible.

Not very helpful and a sweeping statement   The Vishay Si8497db is almost there with a 30VDSmax and a 1.1VGT. I feel sure that a compliant PMOSFET can be found.

Maybe there are exots, but even then you would not pay the price for this application.
Not very helpful and sweeping statement 
There is nothing bad on clamping a logic level mosfet, protection is always good idea.

Who said there was anything bad per se- you are missing the point that the clamping method uses two extra components and puts the gate negative drive impedance up radically. It also increases the quiescent current. You must look at the complete design before making judgements and giving advice.

If "a pmosfet" includes paralleling of devices, then I now own a box of cigars 

If you are saying that you can do the job with two PMOSFETS you would only get half a box of cigars, but you would have to at least name the devices.

You mean GaN Mosfets? Think they are used for low voltage high power rf applications.

I know for a fact that that they are used in normal applications. I asked if anyone had any experience of using them.

By the way, and I mean this genuinely, why don't you have a go at designing a POD circuit- the more the merrier.

[MiDi]

My apologies that the response does not satisfy your expectations, but for several reasons I do not want to dive deeper into it.

Indeed I designed, built and tested PODs many years ago, but it seems my knowledge and experience has gone by to many format c: parties...

To be honest, I feel an undertone in your posts, which does not motivate me.

[spec]

My apologies that the response does not satisfy your expectations, but for several reasons I do not want to dive deeper into it.

Indeed I designed, built and tested PODs many years ago, but it seems my knowledge and experience has gone by to many format c: parties...

To be honest, I feel an undertone in your posts, which does not motivate me.

Please do not take anything personally- just focus on the technical side. Didn't you like my first post to you?

[Zero999]

Here's the TL431 circuit. It will not work very well if the load resistance is high, but there are ways round that.

[MiDi]

I am wondering how this magic circuit works without having the minimum cathode current on TL431.
Could you enlighten me, please?

[Zero999]

I am wondering how this magic circuit works without having the minimum cathode current on TL431.
Could you enlighten me, please?

It doesn't. I put R4 in the wrong place. It should go between the gate and source.

[MiDi]

There are special TL431 with much lower minimum cathode current, could worth a look at 

[MiDi]

E.g. TI has an advanced tl431 with minimum cathode current of 35uA.