Discreet startup delay?

[FlimFlam89]

Hi!

I need to make a delay for a project of mine. The delay has to keep a microcontroller disconnected at startup and after 2s it will make the power go through the micro controller. I’ve tried using a PNP but I don’t know how to make the delay...

Could anybody enlighten me?

[The March Hare]

First though would be why can't the micro be powered as opposed to simply delaying it's intended function with code?

Simple R/C delay might work for you (for example, charge a cap connected to a reset pin through a resistor .. though at the threshold voltage of the pin, depending on the pin, sometimes hairy results can happen, possibly requiring a Schmitt solution). The good old 555 can be implemented as well. A jelly bean comarator and two resistors. There are literally hundreds of ways to do this, the solution usually a matter of what's on your bench, board real estate, power requirements, and dollars (The latter, there are two lead thermal delays available - but they're somewhat exotic and expensive).

Jimbo.

[FlimFlam89]

The thing is that this is all connected to a 4-20mA current loop and the instrument will not work unless it can start up on its own without having the micro attached. Once it’s booted up it can run without a problem regardless if a micro is in line with it.

Since this is a current loop I want to drag as little power as possible, this is a school project/ one off so cost isn’t an issue but id like to keep it "jelly bean"!

[The March Hare]

How many lines on your data loop? And I assume the micro has it's own supply? If you don't mind moving parts you could put a small relay in series with your data line and use one of the micro outputs to hold it open until your delay is satisfied via code - if you happen to have a low powered reed on hand could be a one component solution.

Not really certain what you're up to but keep in mind you're not going to want a chip unpowered with data on I/O pins. Your micro won't tri-state?

Otherwise, if it's a matter of just holding an interrupt I'd probably either charge a capacitor through a resistor on the front of whatever comparator you have at hand configured as a Schmitt trigger - 5 components total I think - or a stand alone 555 which may or may not then need a signal transistor to satisfy the interrupt logic.

[MiDi]

If little power is of concern and it does not matter if it is delayed 2s or 5s, a p-channel mosfet in 12V line could fit.

The threshold voltage of particular mosfet is starting point for calculation of RC network rise time.
The maximum resistance should not exceed 1Mohm, depending on particular gate and capacitor leakage current.
Now you can calculate the capacitor out of the results.
The threshold is temperature dependent, so calculate for worst case high temperature of mosfet and capacitor.

The formula to calculate (you have to solve it to RxC):


Where:
Vc is the voltage across the capacitor = threshold of mosfet
Vs is the supply voltage = 12V
t  is the elapsed time since the application of the supply voltage >= 2s
RC is the time constant of the RC charging circuit

source


There is a problem with this circuit when turning off the powersupply, but there is a simple solution 

[spec]

Hi  FlimFlam89,

How do you want to do this:

[1] transistors, resistors, capacitor diode.

[2] logic chip, resistor capacitor diode

[3] opamp/comparator resistors, capacitor, diode


By the way, #2 is the best

[rhb]

Don't beat your head against a wall.  Use a 555 and move on to the next problem.

[spec]

Don't beat your head against a wall.  Use a 555 and move on to the next problem.

Could you post a schematic. I have never been able to get a satisfactory startup delay circuit with a 555.

[Zero999]

Don't beat your head against a wall.  Use a 555 and move on to the next problem.

Could you post a schematic. I have never been able to get a satisfactory startup delay circuit with a 555.

Post a schematic of what you've already tried and we might be able to suggest where you've gone wrong.

Going back a bit:

The thing is that this is all connected to a 4-20mA current loop and the instrument will not work unless it can start up on its own without having the micro attached. Once it’s booted up it can run without a problem regardless if a micro is in line with it.

Do you know why?

Perhaps that should be fixed, rather than adding a separate timer circuit.

[spec]

Don't beat your head against a wall.  Use a 555 and move on to the next problem.

Could you post a schematic. I have never been able to get a satisfactory startup delay circuit with a 555.

Post a schematic of what you've already tried and we might be able to suggest where you've gone wrong.

I have already asked rhb for a satisfactory 555 circuit, so I cannot see the purpose of your rather patronizing statement. If you posted a satisfactory circuit that would be a much more constructive way to illustrate where I have gone wrong.

[KL27x]

What kind of micro is it?

I'd maybe ponder letting the micro boot up, first, with a low speed internal oscillator and all I/O configured to draw next to nothing... Then have the micro switch the power to the other thing with a transistor. Then go about business. Maybe simply by letting the micro boot first by a millisecond or 10 might solve your problem without jumping thru any additional hoops? (I.e., maybe it's the initial "capacitance" draw of the micro when power is switched on that is causing the other chip to not power up successfully, rather than the quiescent current draw; e.g., try letting them take turns, micro first.) I'm sure you know it, already, but the ramp up of voltage has to be stiff enough and stable enough to get the oscillator in your other IC started... and the micro and it turning on at the same time can cause problems... which your micro would seemingly be handling better (most modern micros have some built in power-good hold/reset circuitry).

For 555, google 555 + one shot and you will find schematics. The 555 comes in CMOS variant with a lower quiescent current than the originals. But honestly, it's dumb for this, because this doesn't need to be very precise. I'd use the LC circuit to bias a FET. Just reading the datasheet and wiring up the 555 and external components (whether by hand or in CAD) would take more time that it's worth. And it will have a startup draw of some magnitude, itself, on top of that quiescent draw. Maybe it is just as bad as the microcontroller.

[spec]

For 555, google 555 + one shot and you will find schematics. The 555 comes in CMOS variant with a lower quiescent current than the originals. But honestly, it's dumb for this, because this doesn't need to be very precise. I'd use the LC circuit to bias a FET. Just reading the datasheet and wiring up the 555 and external components (whether by hand or in CAD) would take more time that it's worth. And it will have a startup draw of some magnitude, itself, on top of that quiescent draw. Maybe it is just as bad as the microcontroller.

Those are exactly the unsatisfactory 555 delay circuits I was talking about. The 555 is a great chip, but it has a couple of missing features that make it unsuitable for quite a few applications. That is why I would like to see the schematic.

I think for pretty much any question you could reply with, "search the internet"

"dumb" is a sweeping statement and meaningless

"start-up draw"  ?

"Quiescent current" ?

[Zero999]

Don't beat your head against a wall.  Use a 555 and move on to the next problem.

Could you post a schematic. I have never been able to get a satisfactory startup delay circuit with a 555.

Post a schematic of what you've already tried and we might be able to suggest where you've gone wrong.

I have already asked rhb for a satisfactory 555 circuit, so I cannot see the purpose of your rather patronizing statement. If you posted a satisfactory circuit that would be a much more constructive way to illustrate where I have gone wrong.

I apologise. I thought I was responding to the original poster. I didn't read it properly. I thought he'd already tried a 555 circuit and was having problems with it, but wouldn't post the schematic. 

Yes,  a 555 circuit is one way to achieve a delayed power on, but I think it's a hack. I believe this relates to a different project with lots of things connected together and a current surge or grounding problem is most likely to blame.
https://www.eevblog.com/forum/beginners/4-20ma-loop-powered-application/msg1961933/#msg1961933

[spec]

Thanks for the reply H99.

I have tried many times to make a decent delay timer from a 555, but the only way to get the function is to use a differentiating capacitor from the supply line, and that is a complete no no for obvious reasons.

I recon the simplest approach is to use an 74HC14 hex Schmidt, capacitor, resistor, and diode.

First person to post the schematic gets the cigar. 

[Zero999]

Why not simply configure the 555 timer as a Schmitt trigger?

[spec]

Why not simply configure the 555 timer as a Schmitt trigger?

Nice version,  The integrating capacitor referenced to 0V is the way.

But the circuit uses nine components (including the mandatory 555 decoupling capacitor across the supply line).

By the way, as you no doubt know, the CMOS 555 would probably be better: no transition supply-line current glitches and very low quiescent current. Also a smaller capacitor and bigger charging resistor can be used.

I am not a big fan of using electrolytic capacitors for timing, except possibly tantalum, because they are lifed and have a relatively large leakage current.  Much better to use a film capacitor.

To be a real smart-arse, I would suggest that a low leakage schottky diode could be used to improve the capacitor discharge at turn off.

The BJT will give a comparatively large voltage drop (CEsat). A MOSFET would fix that issue.

There is also an indeterminate state as the power line ramps up: Q1 base may be at 0V, which will turn the PNP transistor on momentarily before the 555 sorts itself out. This is being picky of course, but it is the kind of thing that can cause odd effects.
And in safety-critical applications, it would not get past the first post because of the transistors dependency on the supply line to be off (the safe condition). In general for SC, the only dependency you can have is 0V (the no power condition).

As you may have guessed, I have had many problems with power on reset (POR) and delay power on (DPO) circuits.
In one instance a quite complex equipment with all sorts of fancy circuits got through the tests, except for a silly little DPO function which nobody thought twice about.

Having said all that, your circuit is well thought out (and drawn) and would be quite suitable for most home electronic projects. The parts are dirt cheap too.

[Zero999]

I agree a Schmitt trigger IC such as the 74HC14 or 74HC1G14 to save space and a MOSFET would be a better option. It would probably be cheaper too. The downsides of the Schmitt trigger IC, compared to the 555 are the threshold voltages aren't so tightly controlled and it's only rated to work off up to 6V.



Yes the dv/dt of the power supply is important for any of these simple circuits to work properly. It's also why I didn't include a supply decoupling capacitor, as I'm not convinced it would do much to help and could be a hindrance, as much as anything.  I wouldn't use any of these circuits in a safety critical application: I'd buy a safety relay with a timer function.

[spec]

Nice 

[spec]

UPDATE (2018_11_28): This schematic is now obsolete: see reply #23 for revised schematic


Below is my latest attempt:

There are no transitions on the output during start-up and there are no dependencies on anything other than 0V... at least that is the intention.

All components are elementary and can be simply analyzed and simulated.

Quiescent current consumption is around 20uA with a 5V input supply.

Turn on is held off until the input supply has reached at least 3.1V which is probably a good compromise for a 5V input supply, but the hold off voltage could be adjusted to suit other input supply voltages by changing D3 accordingly.

[MiDi]

I suggest that this would not work properly, the leakage of Q1ce could lead to uncontrolled turn on of mosfet.
A <=1M resistor from Q1c to Vi+ would fix this.
For improved stability I would add some couple of nF between Q3gs.

[spec]

I suggest that this [POD#4 issue01] would not work properly, the leakage of Q1ce could lead to uncontrolled turn on of mosfet.
A <=1M resistor from Q1c to Vi+ would fix this.
For improved stability I would add some couple of nF between Q3gs.

Thank you for your observations- very helpful

I agree with the reason for the 1M resistor between Q2eb, and it is also good design practice.

But can't understand adding a capacitor Q3gs, because there is already a relatively large parasitic capacitor there by virtue of the PMOSFETs characteristics. Also, it is quite important to turn the PMOSFET on as fast as possible to keep it in the linear region for as short a time as possible.

In fact, I am not altogether happy with the rather long turn-on time constant at the gate of Q3 in the version of the circuit for over 7V supply operation.

Decoupling capacitors etc are not shown so this is not a production circuit, but it is hopefully not far off.

By the way, there is a cigar for anyone who can find a PMOSFET to replace the PMOSFET shown with a VGSmax of 20V or greater, still with a VGth of 1V or less.

And there is a box of cigars for anyone who can find a PMOSFET with the following characteristics:
IDmax: 10A or more
RDss at 3VGS: 5mR or less
VDSmax: 30V or more
VGS: 30V or more (not essential)

Anyone had any experience of these new Nitride MOSFETs?

[Zero999]

Using a zener means the delay will be dependant on the supply voltage, which may or may not be an issue.

Why not replace D3, R4, Q1 and Q2 with the TL431 and add a resistor between the output and C1, to provide the snap-on action and prevent oscillation?

[spec]

Using a zener means the delay will be dependent on the supply voltage, which may or may not be an issue.

That's true of most POD circuits I have seen posted. The solution would be to fit a constant current generator. Most POD circuits are configured to suit the supply line voltage to be used and that is the intention here. But in general, I would prefer comments that are peculiar to this circuit, rather than wade through POD design in general.

Why not replace D3, R4, Q1 and Q2 with the TL431 and add a resistor between the output and C1, to provide the snap-on action and prevent oscillation?

The OP asked for a discrete POD circuit, and, anyway, a complementary transistor bi stable snaps on very fast. Nonetheless, using a T431 is an interesting idea. I have looked at the TL431 before, but the circuit would be less deterministic then. The TL431's relatively large input bias current is also an embarrassment Not sure if the TL431 approach would satisfy the 0V only dependency either. Would the TL431 still have a max 20uA Iq? Never mention oscillations and TL431 in the same sentence: the damn things oscillate for a pass time.

All the same, why don't you do a TL431 POD circuit so I can have a rest and admire your work.

By the way, I thought your idea of using a relay-based POD circuit for safety-critical applications was excellent- I made a note of that.

[spec]

Attached is the POD#4 (issue 03) schematic incorporating MiDi's 1M resistor modification

[MiDi]

But can't understand adding a capacitor Q3gs, because there is already a relatively large parasitic capacitor there by virtue of the PMOSFETs characteristics. Also, it is quite important to turn the PMOSFET on as fast as possible to keep it in the linear region for as short a time as possible.

In fact, I am not altogether happy with the rather long turn-on time constant at the gate of Q3 in the version of the circuit for over 7V supply operation.

Decoupling capacitors etc are not shown so this is not a production circuit, but it is hopefully not far off.

By the way, there is a cigar for anyone who can find a PMOSFET to replace the PMOSFET shown with a VGSmax of 20V or greater, still with a VGth of 1V or less.

And there is a box of cigars for anyone who can find a PMOSFET with the following characteristics:
IDmax: 10A or more
RDss at 3VGS: 5mR or less
VDSmax: 30V or more
VGS: 30V or more (not essential)

Anyone had any experience of these new Nitride MOSFETs?

Capacitor between Q3gs improves dv/dt rating and slows down switching (better emi), think it is not really a concern in this application, but with this high impedance at the gate, me would feel better.

Slow switching would be a problem if you get out of the soa, NDP6020P is capable of DC operation with at least 1A@Vdsmax with appropriate heatsink 

VGSmax of 20V or greater, still with a VGth of 1V or less - would claim it near impossible.
Maybe there are exots, but even then you would not pay the price for this application.
There is nothing bad on clamping a logic level mosfet, protection is always good idea.

If "a pmosfet" includes paralleling of devices, then I now own a box of cigars 

You mean GaN Mosfets? Think they are used for low voltage high power rf applications.

[spec]

Capacitor between Q3gs improves dv/dt rating and slows down switching (better emi), think it is not really a concern in this application, but with this high impedance at the gate, me would feel better.

There is already a fair amount of capacitance at the gate as stated.

Slow switching would be a problem if you get out of the soa, NDP6020P is capable of DC operation with at least 1A@Vdsmax with appropriate heatsink 

You're raising a flag and saluting it. The main reason for a fast switch-on is to get the PMOSFET through the linear region fast to avoid potential oscillations: nothing to do with SOA or TJmax. With an application like this you have no idea what will be connected to the drain of the PMOSFET- could be inductive, capacitive, negative resistance or a combination of all of these and others.

VGSmax of 20V or greater, still with a VGth of 1V or less - would claim it near impossible.

Not very helpful and a sweeping statement   The Vishay Si8497db is almost there with a 30VDSmax and a 1.1VGT. I feel sure that a compliant PMOSFET can be found.

Maybe there are exots, but even then you would not pay the price for this application.
Not very helpful and sweeping statement 
There is nothing bad on clamping a logic level mosfet, protection is always good idea.

Who said there was anything bad per se- you are missing the point that the clamping method uses two extra components and puts the gate negative drive impedance up radically. It also increases the quiescent current. You must look at the complete design before making judgements and giving advice.

If "a pmosfet" includes paralleling of devices, then I now own a box of cigars 

If you are saying that you can do the job with two PMOSFETS you would only get half a box of cigars, but you would have to at least name the devices.

You mean GaN Mosfets? Think they are used for low voltage high power rf applications.

I know for a fact that that they are used in normal applications. I asked if anyone had any experience of using them.

By the way, and I mean this genuinely, why don't you have a go at designing a POD circuit- the more the merrier.

[MiDi]

My apologies that the response does not satisfy your expectations, but for several reasons I do not want to dive deeper into it.

Indeed I designed, built and tested PODs many years ago, but it seems my knowledge and experience has gone by to many format c: parties...

To be honest, I feel an undertone in your posts, which does not motivate me.

[spec]

My apologies that the response does not satisfy your expectations, but for several reasons I do not want to dive deeper into it.

Indeed I designed, built and tested PODs many years ago, but it seems my knowledge and experience has gone by to many format c: parties...

To be honest, I feel an undertone in your posts, which does not motivate me.

Please do not take anything personally- just focus on the technical side. Didn't you like my first post to you?

[Zero999]

Here's the TL431 circuit. It will not work very well if the load resistance is high, but there are ways round that.

[MiDi]

I am wondering how this magic circuit works without having the minimum cathode current on TL431.
Could you enlighten me, please?

[Zero999]

I am wondering how this magic circuit works without having the minimum cathode current on TL431.
Could you enlighten me, please?

It doesn't. I put R4 in the wrong place. It should go between the gate and source.

[MiDi]

There are special TL431 with much lower minimum cathode current, could worth a look at 

[MiDi]

E.g. TI has an advanced tl431 with minimum cathode current of 35uA.