A couple things:
1. Boards are manufactured in pairs of layers at a time. You want to have balanced copper areas on both sides, otherwise the laminate may warp, causing distortion of the layers, and out-of-flatness of the finished product.
This also limits where you can have different thicknesses of copper -- it's very rare (most likely a custom order substrate!) to have unequal copper thicknesses on such layer pairs.
You do have the freedom to choose which layers are paired together: for a 4-layer board, these are:
Layer Pairs: (1 + 2) + (3 + 4)
Two cores are made (1 and 2, 3 and 4). These are laminated together. The cores can be different thickness, but again should be equal. The cores must be made with equal thickness copper foil. Drilling and plating can be done at this stage to make buried vias. Then the cores are laminated together with prepreg. Finally, the board is drilled and plated. The outer layer copper thickness is usually more than inside, because of the final plating step (which also deposits copper in thru-holes).
Oh, some terminology:
Core: blank "copper clad" stock from the vendor. Comes in standard thicknesses (foil and laminate) and materials (FR-4, Rogers, etc..). Core down to 5 mil is pretty standard as far as I know, so don't worry about being able to make very thin, or very thick, boards.
Prepreg: fiberglass that's been pre-coated (impregnated, treated) with resin. The resins, by the way, are room-temperature-stable, solid, epoxy resins (for FR-4 at least, of course). They melt and set when heated in a press.
Prepreg usually has more resin than core material does, giving a higher dielectric constant, poorer dimensional tolerances, and better fill-in around etched traces. Usually used in thin layers, but can be stacked up to make thick layers, too.
Foil: copper as it comes laminated on the core. Typically 0.5, 1 or 2oz, but other sizes are used.
Plating: electroplated copper, added on top of existing foil or (activated) holes. (Holes that are to be plated, are drilled, then coated with an activation agent, so they will become plated as well.) Can be plated quite heavily, plugging small holes ("copper filled vias") and making some very beefy boards indeed ("heavy copper" of 20oz or more).
And yeah, ounces are standard over here... meaning ounces weight per square foot, IIRC. Just substitute "1oz" with 35um (and so on) for the actual metric measurement.
Anyway:
With a layer-pairs build, layers 2 and 3 can be quite close together, using a thin prepreg to glue the two cores together, which is nice for power planes. Buried vias connecting between layers 2 and 3 cannot be made in this process.
Internal layer pairs: 1 + (2 + 3) + 4
A core is etched (and drilled and plated, if buried vias are used), then prepreg and additional foil is glued on top and bottom. The outer layers are etched, drilled and plated. This is the most common process.
A typical 4-layer proto build is 1mm core, 0.25mm prepreg and a few 0.1mm's worth of copper foil totaling 1.6mm final thickness. This makes the inner layers quite close to the surface, which isn't so great for plane-to-plane coupling, but is great for signal-to-plane coupling. The best advantage is making 50 to 100 ohm traces feasible with default width/space rules (usually 7 mils), which is very suitable for the most common CMOS and LVDS type signals.
More terminology: Z0 is the characteristic impedance of a trace. A trace over ground has equivalent (series) inductance and (parallel) capacitance. The ratio of these corresponds to the impedance: Z0 = sqrt(L/C).
Transmission line theory is very useful. You don't have to decompose a circuit board into L and C components; instead, you design it in such a way (namely, using solid ground planes, so the outer signal layers are microstrip transmission lines) that it can be analyzed as simple transmission lines, and then you only need to know Z0, length and velocity factor to solve for interfaces at the transmitter and receiver. Z0 can be calculated from the trace width and dielectric thickness, velocity from the laminate material, and length computed from the CAD files.
This applies to circuit design in, broadly speaking, oh, the 50MHz to 20GHz+ range. Note that that includes harmonics; a signal can be switching at 1Hz but still have signal quality problems when its edge rate is fractional nanoseconds! Typical transmitters and receivers respond in a few nanoseconds, making signal quality a concern even for some Arduino projects, for example.
So, having considered manufacturing -- if we're making that "1010" board, maybe we hatch the planes to balance their copper densities against the signal layers (they are only paired with signal layers -- in either type of 4-layer build). And we flood the signal layers with ground fill.
Now we have some other considerations. Suppose the board is relatively large, and we have some high speed signals that need to be matched impedance, high speed USB say. We could route them on the top layer, but we gain no advantage from our build -- we have two options, microstrip (top layer) and stripline (a trace surrounded by dielectric and then ground, mid-bottom layer). If we route it on the inner signal layer, we need to make sure the dielectric thicknesses are at least enough that a minimum width trace meets the required impedance.
Impedance calculators are easy to find -- there's a number of good ones here:
https://chemandy.com/calculators/microstrip-transmission-line-calculator-hartley27.htmNote that, unless we do blind vias (a hole is drilled partially into the board, but not all the way through, and then plated), every via we make will be from top to bottom, leaving a hole in the bottom ground plane and leaving a stub (if a short one, ~0.5mm) on our signal line. This won't matter until very fast signals indeed (10s of ps), but is a bit of a bother, and the exposed signals on the bottom side can lead to more RF leakage (emission or susceptibility) than desired.
By the way, putting signals on inner layers is tempting from a signal quality standpoint (lots of shielding!), but rather inconvenient to realize, due to the fact that components still have to be mounted on the surface, sooner or later.
This may've been obvious enough that you didn't list it. So, here it is for completeness.
Obvious though it may be, it is sometimes done. Tektronix did this fairly often in the 80s, it seems; it makes their boards very difficult to repair, unfortunately (you can't follow a signal around its trace, it disappears into the board right away..). Where components don't need to be crammed together at maximum density, it does indeed provide shielding for the signals; it also keeps traces away from environmental contamination, except for that little bit connecting to a component. A layer of conformal coating helps more though.
Tim
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