Do I understand this circuit correctly? Timing is weird (3.99C tAoE)

[Moriambar]

Hello!
I am here again with my study of tAoE. This time I think I understand the circuit (see pic below, otherwise is pic 3.99C), but I don't know about the timing.

So what I'm thinking is this. I will exclude the pass transistor (Q3) from the analysis since it's simply driven by Q2.
Startup
The gate of Q1 is high, due to the 220k pullup R3. this makes its drain low since it's pulled down by R2, and so Q2 is off. This means that no voltage is dropped across R3 or R4. C1 is discharged so both of its terminals sit at GND.

First button press
When the on/off button is first pressed current rushes through R3 to C1. Actually the voltage that "wants" to be set at the nongrounded terminal of C1 is given by the divider formed by R3 and the series of R1 and R2 (at least until Q1 starts conducting). Since R1 is big wrt R3 it's almost negligible I think (around 2%?).
Anyhow now this voltage is dropped across R3 with two effects: one is charging  the cap, the other is pulling Q1's gate. So Q1 starts conducting and pulls its drain high. This should have two effect: one is basically pulling up the R1 right terminal, so that current charges the capacitor even through that resistor, and second Q2 starts conducting, thus pulling low its drain.
Now the R3 and R4 split the rail voltage roughly in half.
When the button is released the capacitor stays charged/trickle charges through R1 (actually I think that it discharges a bit through R1 and R2, and then recharges through R1) andQ1 keeps conducting due to its gate being at -Vcc/2 wrt its source.

Second button press
With the second button press C1 which is at vcc, gets connected to Q1 gate which starts shutting down; in the meantime C1 discharges through R4 to ground. But Q1 shutting down shuts down Q2, thus restoring the original condition.

questions
I recreated the circuit (albeit with a different p-fet for Q1) and I measured with the scope the charge and discharge time of C1, finding a ~1us of charging time and around 500uS of discharge. I cannot find why though. I mean no RC value gives me that. I mean, I understand that the charging is done kinda regeneratively so it "rushes", but I don't understand the timings.

Second, I think my analysis is wrong, just because when the cap is discharged, it should start charging up again, since we're in the starting condition.

Can someone please help me? Cheers

[ledtester]

I presume the switch is a momentary switch.

The way I see it...

Let's assume that we are in the on state, i.e. Q1, Q2 and Q3 are all conducting, the push button switch is off and C1 has been charged up to near Vbatt via Q1-R1.

If you momentarily close the switch, the high voltage on C1 will turn off Q1 which in turn shuts down Q2 followed by Q3. No current will pass through R3 so Q1's gate will remain high. C1 will start discharging through R1-R2, but the voltage it presents on Q2's gate will be less than the voltage on C divided by 50 so Q2 will remain off. Eventually C1 will completely discharge.

If instead you hold the switch down, then again Q1 and Q2 (and consequently Q3) will shut off. The voltage on C1 will remain high because it started high and it gets replenished via R3. It will settle down to Vbatt * 10.2/10.4 or 98% of Vbatt. The voltage drop over R3 will be at most 2% of Vbatt which won't be enough to turn Q1 on. Like in the previous situation, because of the voltage divider R1-R2 the voltage on C will never be enough to turn on Q2, so both Q1 and Q2 remain off. When you release the switch you go to the previous scenario.

Again, let's say that the transistors are off and C is fully charged. In order to be able to turn everything  on again, C only has to discharge to Vbatt + V_GS(Q1). (Note V_GS(Q1) is < 0.)

[Moriambar]

Right, thanks!
I get it now