Do packages (sop, ttsop) have internal ground plane? (routing on 2 layer boards)

[John Celo]

When I draw my 2layer boards I always try to have unbroken ground reference beneath, but sometimes I end up routing below packages, and in between the legs of sop packages.

Do these packages have a "hidden" internal ground plane in them that isolates them from traces beneath them on the pcb?
How do I reason about this?

QFNs obviously often seem to have the ground right under them on the package.

But what about LQFP, SOP, TSSOP, DIP, etc? Can I assume they have a ground plane in the package and just route beneath them?

What are the internals of these "black boxes"?

How are they bonded, etc? How do I think about them?

[Zero999]

Sorry, I don't know what you're taking about.

What do you  mean by internal ground plane? The underside of most packages is just an insulator, unless there's a thermal pad, which is often, but not always the negative pin.

[John Celo]

Well, it is a black box.
You know there's a ground pin (sometimes multiple, but less common for sop, ttsop packages).
And you know there's circuitry inside.

If you make a PCB in which you can plug in a rp-pico or stm32 devboard, that board you are pluging in isn't a black box, because you can see the traces, the ground plane (most devboards are 2layer), you can see the ground pins and where and how they are connected.

Similarly if you have an IC (whatever 74hcXXX series or stm32g030 in tssop package) there is a circuit in there, I don't know what-how-and-where is routed internally - It could have a ground plane, or it might not have anything like it, it could have all sorts of things. I don't know. I can't see it. I can't reason about it.

QFNs are less mysterious (see attached pic), since they often have the exposed thermal pad which doubles as ground. So that question is answered right there from that observation.

[PGPG]

Can I assume they have a ground plane in the package and just route beneath them?

You certainly can't assume they have anything else then small chip (like 1x1 or 2x2 mm) in their center connected with very thin wires to pads. Microcontrollers in TQFP packages I use have VCC/GND pairs at each side just because the internal 2 wires going paralel cancels external disturbances as much as possible and they couple to each other (like in common mode choke).

But I have never cared of going with track under them. For microcontrollers my solution is to go under it with VCC and then distribute it radiantly (through corners and all VCC pads) for other ICs just go with signals under them.
My example you can see here:
https://forum.kicad.info/t/approaching-pcb-track-routing-for-a-newbie/36302/8
There is uC with VCC under it and (to the right) other IC (Serial Flash memory) with few SPI signals going under it.

[AndyC_772]

But what about LQFP, SOP, TSSOP, DIP, etc? Can I assume they have a ground plane in the package and just route beneath them?

No, these packages don't contain a ground plane. The copper leads are basically just solid wires that taper down towards the die, where they connect to it via the bond wires, which are very thin, short, and usually made of gold.

One of the reasons BGAs are so much better is that this copper lead frame doesn't exist, and the connections between the board and the die are much shorter. This *really* matters with high speed signals like DRAM.

However, if you're using a 2 layer board, then I'd assume you're not dealing with high speed signals or anything particularly suspectible to noise - and in that case, feel free to route your signals wherever is convenient.

If that's not the case, and your designs do include some fast or sensitive signals, then you should be using at least a 4 layer board. There's no reason not to. Depending on what ICs you're using, and what the signals are, you may wish to avoid routing under SSOPs and the like, but we're outside the scope of a 'rule of thumb' here. You need to consider the actual signals, edge speed, noise margin, and so on.

[Simmed]

When I draw my 2layer boards I always try to have unbroken ground reference beneath, but sometimes I end up routing below packages, and in between the legs of sop packages.

Do these packages have a "hidden" internal ground plane in them that isolates them from traces beneath them on the pcb?
How do I reason about this?

QFNs obviously often seem to have the ground right under them on the package.

But what about LQFP, SOP, TSSOP, DIP, etc? Can I assume they have a ground plane in the package and just route beneath them?

What are the internals of these "black boxes"?

How are they bonded, etc? How do I think about them?

you are asking about the lead frame ? and die wire bonding ?
you can find it on google
and there is these threads
https://www.eevblog.com/forum/projects/different-die-pictures/

and some entire (rejected product?) wafer for sale too 

[John Celo]

Analog switches, for example, most commonly come in sop/tssop (4051, 4052, 4053 series, etc)

If these (tssop, sop) packages don't have a ground plane, wouldn't that mean that - on a 2 layer board (any layer board for that matter!) - it would be best not to route under sop/tssops/LQFP packages if possible, but have unbroken top layer groundfill section exactly underneath those ICs?

And if necessary to route signals via bottom 2nd layer plane, if they have to cross the IC?

then you should be using at least a 4 layer board. There's no reason not to.

I'm very cost sensitive. The difference in price isn't big, but it's still there for larger pcbs.
All I can do is go from 1.6mm to 1mm pcb thickness which doesn't change price. (if the pcb isn't subject to significant mechanical stress)

The images of "leadframes" (see-pic attached) give a good idea of how to reason about this. If there is "ground plane", it looks like it's only right underneath the die which makes up a very small area of the whole package, and the very lengthy leads are mostly uncovered by anything.

The DIP image makes the most extreme example, but it looks like it's safe to assume that most legged packages will have very, very small silicon die, and the leads will take up rest of the area.

I feel like I have a tiny bit better understanding of this now.

[Kharn_the_Betrayer]

What are the internals of these "black boxes"?

How are they bonded, etc? How do I think about them?

As you found later in the thread, the internals are really just a silicon die with leads coming off. The dies are manufactured using a form of microlithography (https://en.wikipedia.org/wiki/Microlithography). I've never heard of an IC having an internal ground plane, though I haven't seen everything and so I won't say it's impossible.

As others have mentioned, routing traces under ICs and especially in between pads is a bad idea when dealing with high-speed signals, but it's also a bad idea from a circuit protection point-of-view. I like to keep around 1.5 mm of space in between conductive material where possible (i.e. not diff pairs, or near IC pads).

[MarkT]

The bulk of an IC wafer (sometimes called the substrate, although that can mean other things), is usually a single circuit node underlying all the active circuitry.   That probably has some screening effect.