120kHz oscillation in received DALI signal

[ocset]

Hi,
We have a DALI communication setup. To be brief, DALI is basically square wave transmissions at 1200Hz.
A DALI bus is pulled down and released at the 1200Hz frequency, as in the attached schematic. (LTspice sim also attached)

In our DALI circuit, the node RA3 is following the transmission of the DALI bus, and is obviously an inverted form of it…however, within the high-going pulses at RA3, there is an approximately 120kHz oscillation….which is rendering the comms not working.

I believe that this 120kHz oscillation is caused by the fact that due to the bridge rectifier, the DALI bus is not fully getting actively pulled down (after the bridge) for the “Low” pulses, and therefore the NPN at RA3 is turning on and off repeatedly at 120kHz as its base current starts to fall to around its off level.

Would you agree, that the best way to stop this oscillation would be to reduce the Base_emitter resistor down to 1k? (This would also mean reducing the resistor R18 down to 2k2 so that the voltage isn’t divided down so much. R18 and R19 are 0603 size)

The attached simulation doesn’t show this unwanted 120kHz oscillation happening.
(by the way, there is also a 60W offline led driver SMPS on the same PCB as the DALI receiver part of the circuit shown)

[ocset]

By the way, the attached shows the  120khz noise we are seeing at RA3.
Top is what it should be, bottom is what we get

This shows (on pg 3), the DALI idea we took our circuit off
http://ww1.microchip.com/downloads/en/AppNotes/01465A.pdf

[dmills]

Read the actual DALI spec man!

There are rise and fall time requirements, which you clearly don't meet, at least if your thing is using literally that spice circuit.
There are also isolation requirements.... (And as a QOI issue you probably want to make the thing proof against getting mains up it, somebody will cock it up that way).

120kHz is a really odd frequency for something like this to take off at, so I am suspicious, what frequency is your switcher running that drives the LEDs? Also is this noise just on the receiver output or are you also seeing it on the DALI bus (Could be the transmit circuit or even the current source oscillating)? 

Now given the presence of that zenner diode the bridge rectifier should be a non issue, but with 10k as base/emitter resistor the current to start that transistor into conduction is only going to be 70uA or so, (0.7V/10k) which feels horribly low for a zenner diode. I would want more like a mA or so down that chain if I was doing it that way, but really there are far more reasonable DALI circuits out there, that is a pathetic attempt. A quick fix would be putting something like a couple of silicon diodes in series with the base to raise the threshold voltage a bit, but really, do it right.

DALI is not a difficult physical layer so I dont really understand why people have so many problems with it.

[ocset]

Also is this noise just on the receiver output or are you also seeing it on the DALI bus

Scoping the DALI bus  at the transmitter output..its clean. No 120kHz oscillation there.
The switcher is variable F(sw)......75-100kHz

There are also isolation requirements

thanks, the DALI receiver is on the secondary side of a fully isolated 60w smps.
The transmitter is powered by a wall wart output with full mains isolation.

but really there are far more reasonable DALI circuits out there, that is a pathetic attempt.

Thanks, but how is our circuit so badly different from page three of this?...
http://ww1.microchip.com/downloads/en/AppNotes/01465A.pdf

I think if the post bridge rectifier DALI bus was getting fully pulled down to ground, then I suspect we wouldn’t have the problem?
..But we initially didnt want to add components to do that as it would have been more cost.

[dmills]

What is it with you and insane (not to say inane) sensitivity to BOM cost?

That circuit is NOTHING at all like the one on page 3 of the microchip datasheet (Which in any case is a demo board circuit and probably not a good idea in real products), for one thing yours has significant gain on the receiver which the microchip circuit does not.

Given your perpetual problems with getting stuff past EMC I would also strongly suggest that providing a large loop for common mode to travel might not be the worlds best plan, I would have the optos back in, also a couple of caps to slow the transmit edges a lot would not hurt anything. 

Regards, Dan.

[ocset]

for one thing yours has significant gain on the receiver which the microchip circuit does not.

Thanks, what about the following adjustment?…now we have reduced the gain of the first NPN stage, making it a follower. We have also made the base_emitter resistor 10 times less.
(pdf schem and LTspice sim attached)
On the previous board,  the original circuit of  the top post  worked absolutely fine, but we did not have the bridge rectifier then.

[dmills]

Complicated much?

Also I don't think that meets the 2mA maximum load imposed by the DALI spec at maximum bus voltage.

I would probably have gone with the original (more or less) and just stacked a couple of diode junctions in series with the base connection (And maybe reduced the bottom resistor a bit or added a second one between the diodes and the base).

The objective is to put the switching threshold at about 9V IIRC.

If I was going to blow two transistors on the problem I would be thinking long tailed pair set up as a schmitt trigger, but it is overkill.

Regards, Dan.

[ocset]

Also I don't think that meets the 2mA maximum load imposed by the DALI spec at maximum bus voltage.

Thanks, thats a good point,  sorry  i forgot to say that in this case, there is only one device on the dali bus.

[dmills]

  Then it ain't DALI and you might as well use something trivial serial.

Regards, Dan.

[ocset]

Thanks, the DALI devices that  our customers buy (to use as the transmitter you see in our schem) use DALI so we have to have the DALI protocol.

[ocset]

I would probably have gone with the original (more or less) and just stacked a couple of diode junctions in series with the base connection (And maybe reduced the bottom resistor a bit or added a second one between the diodes and the base).

Thanks, that sounds like the best shot for us. The diode junctions will help because eg 1n4148's have very little leakage, so the leakage thats coming through the zener wont be able to get through the stackjed diodes so easily.
And for that bit of leakage that does get through, the lower value base_emitter resistor will bleed it away.
Thanks.

I am hoping, in the first instance, that we can solve it by  just putting a 3k9 across the dali bus (post bridge) and also by reducing base_emitter resistor to 1k (that means we have to reduce the top resistor to 2k2  so as to reduce the potential divider effect)....these changes we can do without re-spinning the board.
If it doesnt work, then we will have to come in with the diodes on the re-spun board, , and also possibly a base_emitter capacitor of some 1nF.

[ocset]

The attached (pdf schem and LTspice sim) are all the possible ways of fixing this DALI comms (Tx and RX) circuit.....we hope we only have to resort to circuit "A"

[ocset]

by the way, the following circuit also works fine, but we dont want a bulky opto in there as we dont need the isolation.
(ltspice and pdf attached)