Eliminating negative spike from high side switch

[drdm]

I want to design a PMOS high side switch with discrete components, but I run the problem show on figure 3 and 4 of this application report.
https://www.ti.com/lit/an/slva887/slva887.pdf?ts=1635000814249&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FTPS22965
When I turn on the switch I get a not so small negative voltage spike before the output voltage starts to ramp up.
Does anyone know what kind of solution is used inside the integrated load switches to avoid this issue and whether it is possible to implement with discrete components?
One thing that comes to mind is to have a diode in series with the mosfet, but then I'll have a constant drop.

[magic]

It looks like inevitable consequence of gate-drain capacitance, Cgd.
Before the FET turns on, gate voltage needs to decrease by Vgs(th) and then Cgd·Vgs(th) of charge flows through Cgd and gets injected to the output.

You can minimize charge quantity by picking a MOSFET with low gate threshold voltage (logic level) and low parasitic capacitances (but this correlates inversely with RDS(on) most of the time).
You could put a reverse Schottky diode on the output to clamp the spike to ~300mV.
You could spread the effect over time and reduce negative output current by slowing down the slew rate of PMOS gate voltage, for example by adding plenty of resistance in front of the NMOS (driver) gate.

[rfclown]

Figure 3 and 4 are showing a method of controlling the rise time with a capactor from drain to gate, but pointing out a side effect of that approach. I've never used that method. I've made plenty of supply side switches, but I've not paid attention (or ever looked for) negative voltage on the output. Is it something you are actually having trouble with when there is a load on the circuit?

[drdm]

It is not something I have an issue with, but I am curious.
What method do you use for high side switches?

[T3sl4co1l]

I either don't worry about it, or drive the gate slow enough that it isn't much of a problem*, or use a smart switch (which includes level shifting and protection, big improvement).

*How did they do an entire appnote without simply shoving in a stupid gate resistor?  Well, yet more proof that appnotes are a crap shoot.  To be clear, I mean a resistor either in series with the driving (low side) drain (in which case high side Vgs(on) is divided down from the input -- this is useful for situations with high Vin), or in series with the high side gate (in which case turn-off is even slower, because the pullup acts in series with the gate resistor).  Whatever the arrangement, the point is to get a sizable Thevenin equivalent resistance into the gate pin.

The initial-step behavior of their suggestion, is simply normal Miller effect given a nonlinear device (namely, the PMOS isn't amplifying for Vgs > Vgs(th)).  There are two additional reasons why it sucks:
1. The slew rate is limited by the low side's gm or Rds(on).  It's basically drawing short-circuit current through the gate and cap.  So any modest slope (say ~V/ms) takes a fuckoff massive cap, and draws huge startup current (basically shoot-through current -- it flows through both MOS -- except there's a capacitor in series so it tapers off over time).
2. Connecting low impedances to the gate terminal, especially capacitances, is very troublesome in general.  This warning applies to zener diodes** as well as G-S shunt capacitance, as well as Miller capacitance (D-G) shown here.  During the active range (Miller plateau at the gate, slope at the drain), the transistor can oscillate at the characteristic frequency of that loop -- and with gm being so high, it doesn't take much.  I'm not sure how doable this is with small SMTs (you may be able to get away with it more often), but it's commonly seen causing 200-400MHz oscillation in power transistors (notable because TO-220 for example has a whopping ~7nH lead inductance per pin).

**Often, for the resistor-divider case mentioned above (*), a zener is in parallel with the pullup resistor.  This extends the supply range where safe Vgs(on) is applied.

Tim

[magic]

*How did they do an entire appnote without simply shoving in a stupid gate resistor?

Because the point of this appnote is to sell you on their ICs.
Never trust a corporate marketroid.

BTW, shoving a resistor into PMOS gate circuit also reduces output slew rate.
Shoving a resistor into NMOS gate circuit precisely controls PMOS gate slew rate.

[T3sl4co1l]

Not always.  My favorite TI appnote to rag on, is one where they discuss switching loop ringing in an inverter composed of brand-name FETs.  Nothing integrated to help there, just incomplete knowledge on display.

Tim

[rfclown]

It is not something I have an issue with, but I am curious.
What method do you use for high side switches?

I just do like Figure 1 of the app note but have a resistor in series with the gate of the N device. I usually use an NPN for the bottom device. It's usually a microcontroller output switching the thing on and off in the things I've done.

[David Hess]

In precision circuits, charge with the opposite sign would be injected into the output to cancel the negative going pulse.  This can be as simple as a positive going edge coupling charge into the output through a capacitor.

A more likely solution in this case is to bias a diode connected to the about +0.6 volts high so the output cannot go negative at all.