Synchronous Buck Converter Designing

[Nithis]

I tried designing a Synchronous Buck Converter following a tutorial on YouTube as a preliminary step to present to my professor, showcasing basic learning of circuit design for a project. However, I encountered an issue where the current flowing through the MOSFET is excessively high during the switching period, as shown in the attached diagram. I’m quite confused about what might be causing this issue, how to resolve it, and whether my initial design is okay (other performance aspects, such as Voutput and the current flowing through the inductor, align with my calculations).

[Slh]

The pulse on turn off is the reverse recovery of the anti parallel diode. The (smaller) pulse on turn on is the output capacitance of M2 charging up. If you're only after a few amps output then the MOSFETs that you've chosen might be a bit on the large side.

Incidentally, an annoying thing about spice simulation is that the reverse recovery is only partially modelled so reverse recovery losses are higher than your simulation will suggest.

[Konkedout]

It might also be non-overlap dead time.

In the simulation, you could try adding a schottky diode in parallel with the low side MOSFET with cathode to drain.  That might prevent your drain body diode from conducting so prevent diode reverse recovery if that is your problem.  Note that in hardware, even a tiny amount of layout inductance between the schottky diode and the low side MOSFET prevents it from working well.  That is why the FETTKY  (FET with integrated schottky diode) was a thing for a while.

Nowadays I think that controller ICs focus on getting the non-overlap dead time right.

[Nithis]

The pulse on turn off is the reverse recovery of the anti parallel diode. The (smaller) pulse on turn on is the output capacitance of M2 charging up. If you're only after a few amps output then the MOSFETs that you've chosen might be a bit on the large side.

Incidentally, an annoying thing about spice simulation is that the reverse recovery is only partially modelled so reverse recovery losses are higher than your simulation will suggest.

Thank you very much. What you’ve answered has helped me to continue my research and better understand how the circuit works. I’d like to ask just a little more. So, it seems that the current spike from reverse recovery can’t be completely eliminated, but it can only be reduced to an acceptable level (by using a diode with low trr and low Qoss), right?

[Slh]

With MOSFETs, the only thing you can do is optimise more for switching so you'll probably end up with a higher r_ds(on) MOSFET with a faster diode for M1. So yes the spike can't be eliminated, only reduced.

A silly question, are the losses excessive at the moment? Perhaps you can live with it at the current level.