Author Topic: ESD Zeners in this diagram ?  (Read 3632 times)

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Offline kellogsTopic starter

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Re: ESD Zeners in this diagram ?
« Reply #50 on: May 03, 2023, 07:53:39 pm »
No, no more Zener. I am placing a smaller TVS there on the branch with the V_rrm = 300V rectifier.

Maybe a SM6T15AY; It has
V_clamp_max = 27.2V or 21.2V depending on waveform: 8/20 or 10/1000
V_br_min = 14.3V

ISO transient -150V @ 10 ohm @ 10/2000 -> roughly some 13.5A max through that branch; for my rectifier -> some 2.7V = V_f, with V_clamp closer to 21.2V than to 27.2V -> happy FET
ISO transient -220V @ 50 ohm @ ... 0.005/0.015 or 0.005/100 (?). ISO not clear on it -> roughly some 4A max through that branch; for my rectifier -> some 2V = V_f, with V_clamp closer to... probably 27.2V -> a bit stressed FET

I think both the FET and any fuse stay roughly happy :)

Offline kellogsTopic starter

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Re: ESD Zeners in this diagram ?
« Reply #51 on: July 30, 2023, 11:58:49 am »
Yeah, that should be fine.

I would still use the G-S zener.  No need to push limits, and covers for inevitable inductance of the TVS.

Ugh, excuse me, but...

Just had a look over the normalized ZthC for 400 ms and and single pulse - it is around 0.6

RthC = 1.4 C/W and average I ~= 55A (load dump). For Rds ~= 5 mohm:

T_j = 0.6 * 1.4 * 3025 * 0.005 + T_c = 12.7 degrees over case temperature.

But then there is the case-ambient thermal resistance as well, and much bigger. Should I worry about it ?
« Last Edit: July 30, 2023, 01:18:29 pm by kellogs »

Online T3sl4co1l

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Re: ESD Zeners in this diagram ?
« Reply #52 on: July 30, 2023, 07:21:34 pm »
Oh, you probably want a D2PAK then, not one of those PDFN5X6 variants.  I don't know why ZthJC continues going up past 10ms, *possibly* the source bond clip soaking some heat, but in general ZthJC (to *case*) is over and done in a couple ms (here, about 10, less the source clip), and then it's up to whatever's around it.

Which, if you don't have solid metal backing up the tab, that's the end of it, ZthJA skyrockets into the 100ms range.  You need ZthJA to do this estimation, not JC.  (Note, it's no worse than 1:1, or 10x Zth for 10x t, being the constant heat capacity line assuming no new material is being heated.)

Anyway, D2PAK is more material.  Thicker tab.  That's it.  Chip can be identical, same SOA.  Could also use a metal core PCB, or one of those boutique fabs with metal pillars buried into it (or machined or whatever), but... right.

Also, you probably want to do a real simulation, because pulse power varies with time, and so does heat as it's spreading out.  A transient thermal model can be fitted to the curve, and then connected to some manner of heatsink (to the extent one can be turned into a transient model).  You will most likely find PCB alone isn't enough, and a direct clamped heatsink of some substance is required (even just a slug of metal).

Or put the TVS out in front, in series with a rectifier big enough to handle the surge automatically (same idea, it'll just have a higher Tj(max) and thicker leadframe).  Saves MOSFET size.  The rect + FET is going to be bigger than just using a larger MOSFET though.

Note that TO-220 (standing without a heatsink) is about the same as D2PAK, if verticality is any help.  And can be clamped to a slug of metal, or heatsink proper, if needed.

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