Author Topic: Feedback requested for enclosed clock-generator schematics  (Read 802 times)

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Offline bitmanTopic starter

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Feedback requested for enclosed clock-generator schematics
« on: January 16, 2019, 04:22:13 am »
Hello,
I've been working on creating a CPU using 7400 series TTL chips only (except for the 555 timers). It's a fun project which has taught me a lot - to begin with, that drawing lines on a piece of paper isn't even close to what reality looks like when we actually bring components together.  This is my first real schematics - and I would like some input on how to format/display schematics and on the circuit itself.

The build I have has a TON of leds to illustrate how everything from clocks, registers, busses etc. work. The design I have uses 3 shifted clock pulses to complete a full operation. For a while I used simple schottkey diodes to create a delay but that did not give me the ability to manually step through each pulse. So hence this design. The 4th pulse (status) is the idle position - just needed to show/explain what's going on.  I use very simple BJTs to create enough current for fanout to all modules.

A few things that I still am not sure how to implement:
* When manually stepping right now I only have a rising edge since the clock stays active (high) while waiting for the next pulse. I am not sure how to implement this so I can get a falling edge too as part of a manual clock - ie. I need no signal. Some kind of delay when in manual mode on the enable signal is what I think is needed. Not sure how to implement the delay - and worse, that would remove the visual aspect of showing the clock signal, so I'm thinking that's not possible.
* Entering manual pulse may need to reset the clock to phase1. I most likely will just add a swich to set the Rset pin high on the counter, but I do wonder if it's possible to trigger this reset on when the "step" feature is activated? In other words, I just need a short pulse when the signal goes high, and then it needs to stay low.

Note - this is not made for speed :) While I try to keep noise down, this is never going to even get close to the 500Hz I've set the max on the frequency for. The whole idea is having a teaching instrument - for me to learn the physical electronics side, and for others to learn how a CPU actually works. As I get more used to creating schematics I'll eventually get everything else made into a diagram.
 

Offline Kasper

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Re: Feedback requested for enclosed clock-generator schematics
« Reply #1 on: January 16, 2019, 05:41:57 am »
Your schematic is nice and clean looking with the different parts separated into blocks. Net labels help with that and they are nice for reading schematic and for drawing the PCB but it is good to include wire connections also when it is feasible without making a big mess.  Wire connections make it easier to see how everything connects without having to read all the net labels.

For example, auto and step in the top middle and top left should be connected.

Also it is good for current to flow from top left to bottom right.  For example, auto and step in the top middle should be mirrored across y axis.
 


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