### Author Topic: FET on opamp output, how to remove oscilations?  (Read 5995 times)

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#### junits15

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##### FET on opamp output, how to remove oscilations?
« on: December 22, 2016, 06:03:57 pm »
Hi all!
I've been working on a project lately and I've run into a roadblock that I'm not really sure how to get around.  To give some backstory, I came across the simple constant current load design floating around using an op amp and a FET with current feedback, like the circuit shown below.

I thought it would be fun to make this into a constant power load, so I used an AD633 analog multiplier IC to measure the power and create power feedback.  My circuit is shown below:

The theory is this:
input voltage is measured and divided by 10, input current is measured divided by 10 and sent inverted into the AD633.  The multiplication is done inside the chip, giving a value that is equal to (P/100).
Before the signal is sent out of the 633 its divided by 10 again to give (P/1000)
This is then multiplied by 10 and divided by 2 to give (P/200), which swings from 0 to .6.  With .6V corresponding to 120W being dissipated.  I've picked 120W as the maximum power setting for the circuit.  the reason for dividing by 2 is so that the same potentiometer can be used to set constant power as can be used to set constant current.  The current measurement was intended to swing between 0 and .5V (corresponding to a 10A maximum).  If the power measurement was not divided by 2 at any point it would swing from 0 to 1.2V.  In current mode that would mean a max input current of 24A, which is more than I need for this and would complicate the design.

However the thing oscillates like crazy when in constant power mode.  The switch S1 picks weather the device is in constant power or constant current mode, up is CI, down is CP.  C3 and R4 were used to remove the oscillation in CI mode, however I didn't pick those values and I'm not sure why that setup works.  I saw that it was included in someone else's design and that it would remove the oscillations at the gate.  Since I don't understand why this works I'm not able to apply this idea to the CP mode of the circuit.  At first I thought it was a simple RC filter, but I'm now beginning to think that all that is happening is that the cap C3 is allowing the oscillation to be fed back to the amp and therefore removed.  I'm not sure about that though because when adding a similar fixture to the constant power mode, which basically means always having C3 running between the output and the inverting input the oscillation was still present.  The capture below shows the gate voltage when the system is oscillating:

I'm not really sure what to do to proceed, my only though is that I somehow need to filter the output of the opamp so that any oscilation will never make it tot he gate of the FET, but i'm not sure how to do that given that the FET poses a capacitive load to the opamp output.  Any help would be really appreciated! This is a project I've been working on and off on for a long time and It's killing me that I've put so much work into it only to have it not work as intended. Thank you in advance!

Also! You may disregard the Zener D1, it only serves to be a rough "maximum current" limit for the device.  Essentially just limiting the gate voltage to limit the maximum allowed current in constant power mode.
I'm thinking for the sake of simplicity I should set the maximum power limit to be 100W just to make things simpler for calculations.
« Last Edit: December 22, 2016, 06:18:07 pm by junits15 »

#### orolo

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##### Re: FET on opamp output, how to remove oscilations?
« Reply #1 on: December 22, 2016, 08:06:30 pm »
I'm not an expert, but what I'd try is the following: if you fed back U1A with 100nF and it still oscillated, the problem should be in the other amplifiers. I'd bypass the feedback resistors in the non inverting amplfiers (R3 and R9) with capacitors. It is good practice to always do that with a small capacitance, to avoid ringing or oscillation. See:  https://e2e.ti.com/blogs_/archives/b/thesignal/archive/2012/05/30/taming-the-oscillating-op-amp .

Maybe the problem is elsewere, but I'd not consider myself safe with those amplifiers unbypassed.

#### Kleinstein

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##### Re: FET on opamp output, how to remove oscilations?
« Reply #2 on: December 22, 2016, 08:17:10 pm »
The constant power loop still needs a kind of "filtering", that is a point to make sure the loop gain for that loop rolling off to high frequencies in a controlled way, without to much phase shift. This usually means one first order low pass filter and everything else relatively fast. Adding a little filtering at many places is usually bad as this would be a higher frequency higher order filter and thus a lot of phase shift. The simple way is one really slow stage and the rest should be fast - this may even mean using faster OPs than the OPA277.

So one would need an equivalent to the C3 / R4 part of the constant current control loop.

There are at least two options to do that:
1) have a separate R/C combination similar to C3/R4. This could be for example by reusing C3 as well and have a resistor between U4A-output and U1A-input.

2) Use the current control loop as a kind of fast inner loop. This could be done by using U4A as an PI-regulator: add a cap in series to R9 and the power-setpoint to the inv. input. The output of U4A would than work as the set current.  In this case it would be necessary to make C3 considerably smaller to get a much faster current control (e.g. more like 100 pF-1nF for C3).

Power control could be difficult with some sources. One might need to adjust the gain, depending on the load / set-point. As the regulation is nonlinear this is not an easy problem. If might be a good idea to try it in a simulation first. One might need a different solution to make it work with complex power sources over a large range - this could mean making the roll of frequency dependent on the voltage range.

Already for current control there should be an RC snubber at the output. So something like 10 Ohms and 1 µF in series.

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#### danadak

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##### Re: FET on opamp output, how to remove oscilations?
« Reply #3 on: December 23, 2016, 01:24:52 am »
Just looking at the closed loop signal path you have quite a lot of phase
shift, especially the MOSFET used in the current source.

One way to look at this is to open the loop, then stim with an edge or pulse,
and look at time domain response. If you see a lot of ringing then you know
your phase margin.g will be a challenge, especially when you then throw in
G via closing loop.

I would look at each "section" and examine its phase margin. Or use simple
models of each section, spice it, and see where largest problems occur. Or with
simple models do an s plane analysis of the open loop for starters. See what
phase margin that results in.

Regards, Dana.
Love Cypress PSOC, ATTiny, Bit Slice, OpAmps, Oscilloscopes, and Analog Gurus like Pease, Miller, Widlar, Dobkin, obsessed with being an engineer

#### BrianHG

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##### Re: FET on opamp output, how to remove oscilations?
« Reply #4 on: December 23, 2016, 02:37:47 am »
Well, if you don't need the response speed, try switching the OPA2277A with an OP07, shrink R2 to 27 ohm series resistor and get rid of C3.  I've done something similar around 20 years ago, though it was a class A audio amp, the higher speed OP27GP I used at the time also oscillated.  The slower OP07, at the time, with their spec in the data sheet which said 'Guaranteed not to oscillate under large loop delay' did work, but, my full scale audio bandwidth was only around 10Khz.
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#### Kleinstein

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##### Re: FET on opamp output, how to remove oscilations?
« Reply #5 on: December 23, 2016, 09:44:05 am »
R2 is about right at 100 Ohms. C3 is somewhat needed to prevent possible oscillations in current regulation. The shown value of C3 is just very large and thus slows the current loop down a low. It is better to use a fast OP and C3 (preferably smaller) than a slow OP.

It is a good idea to do simulations of the circuit parts separately. To understand where phase shifts occur.

#### orolo

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##### Re: FET on opamp output, how to remove oscilations?
« Reply #6 on: December 23, 2016, 02:12:32 pm »
I've given a try to simulating the circuit. I don't have models for OPA2277, so I decided to use the OP07 provided by LTSpice. For the mosfet I chose an Si7164DP (I think almost any big mosfet can play the part), and instead of the multiplier I used an arbitrary voltage source. I had to implement a division by 10 in the voltage multiplier (I think you mentioned that), and I also had to invert the output (since both U2A and U2B are noninverting). Given that, the circuit works as intended: if you run the simulation, for 1 millivolt at the + input of U1 you get a dissipation of 199.01mW at the load.

Well, at least this spice model proves that the concept is right. Perhaps playing a bit with the feedback loop the reason for oscillation will come out.

#### Kleinstein

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##### Re: FET on opamp output, how to remove oscilations?
« Reply #7 on: December 23, 2016, 03:55:43 pm »
For a first simulation one can use the universal OP model and set the GBW / slew rate accordingly.

There is a principle problem with this simulation: it assumes a kind of low Z source, so that more current means higher power. One you are below a certain voltage, the power vs current curve turns the other way. With just a voltage source with output resistor this is at half the voltage. So regulation will not work for higher current - if will just run to a maximum current.

It would likely be a good idea to have an adjustable current limit also in place, so that the either the power or the current sets the limit, with automatic change over between constant current and constant power. This would be similar to a lab supply with CC and CV modes.

#### orolo

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##### Re: FET on opamp output, how to remove oscilations?
« Reply #8 on: December 23, 2016, 06:22:38 pm »
There is a principle problem with this simulation: it assumes a kind of low Z source, so that more current means higher power. One you are below a certain voltage, the power vs current curve turns the other way. With just a voltage source with output resistor this is at half the voltage. So regulation will not work for higher current - if will just run to a maximum current.
I see, the problem is underdetermined. Disregarding losses in the current sense resistor, the bulk of the losses happen in the mosfet. Since power dissipated equals V_ds·I_d, that represents a hyperbola in the transistor's Gummel plot. That hyperbola will act as a kind of load line for the mosfet, who will be able to slide along the hyperbola, usually to the point of cutoff or saturation. So another restriction is needed to insure a stable operation point for the transistor; constant power per se is not enough. Otherwise, any point of operation will be unstable.

Edit:

Well, not absolutely undetermined. Let's see, if the source voltage is 12V with a source resistance Rs, we have two equations:

V_ds · I_d = p               (constant power)
V_ds + I_d · Rs = 12     (voltage source)

Solving for I_d:

(12 - I_d · Rs) · I_d = p

Rs·I^2 - 12·I + p = 0

A second degree equation. So there will usually be two operating points for the circuit. For example, for a 100 Ohm source resistance, and 200mW power (the simulation), the equilibrium currents are i1 = 20mA, and i2 = 100mA. In fact, repeating the simulation for various starting points, there is the 20mA equilibrium, and there is other equilibrium with the transistor saturating at 120mA (This is exactly what you meant in the quote-- the higher equilibrium current is an unstable equilibrium, and if it is surpassed, the fet goes into full conduction and doesn't regulate).

So the problem is undetermined after all, and not very stable.

For high source resistances, the second degree equation has no solution and the transistor just acts closed switch and leaves the full load to the sense resistor. There are no equilibrium currents, and there is no correct power loading. That's natural-- 200mW can't be extracted from source resistances high enough.
« Last Edit: December 23, 2016, 07:24:58 pm by orolo »

#### Kleinstein

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##### Re: FET on opamp output, how to remove oscilations?
« Reply #9 on: December 23, 2016, 08:32:01 pm »
Depending on the source there are often two solutions. Usually you want the electronic load to go for the lower current that delivers the desired power. For this one the regulator could work this way (at least in principle - still pending frequency compensation). For the other (high current) solution it will not work.  With a nonlinear C/V curve for the source there may be only one, more than two or maybe no "solution" to get a given power.

The possible instability is known from SMPS. In first approximation they are a constant power load at there input side. In some cases they can get unstable / lock up - usually a kind of under-voltage lockout is used to prevent this on start up.

Normal there is little danger for the load current to go to high, but in rare cases it might be possible. To prevent the load form going too high in current, it might be good to also have an adjustable upper limit for the current.

The other operational mode for an electronic load would be a simulated resistance.

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#### junits15

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##### Re: FET on opamp output, how to remove oscilations?
« Reply #10 on: December 23, 2016, 09:44:25 pm »
Wow! I did not expect so many replies! Thank you all!

I'm not an expert, but what I'd try is the following: if you fed back U1A with 100nF and it still oscillated, the problem should be in the other amplifiers. I'd bypass the feedback resistors in the non inverting amplfiers (R3 and R9) with capacitors. It is good practice to always do that with a small capacitance, to avoid ringing or oscillation. See:  https://e2e.ti.com/blogs_/archives/b/thesignal/archive/2012/05/30/taming-the-oscillating-op-amp .

Maybe the problem is elsewere, but I'd not consider myself safe with those amplifiers unbypassed.
I think that Would be a logical place for me to start, I was able to have some luck by adding a bypass cap to the input of the current sense noninverting amp, but I think it would be better as you said in the feedback loop of that amp.  I think my next step will be to add more bypassing to the circuit.

The constant power loop still needs a kind of "filtering", that is a point to make sure the loop gain for that loop rolling off to high frequencies in a controlled way, without to much phase shift. This usually means one first order low pass filter and everything else relatively fast. Adding a little filtering at many places is usually bad as this would be a higher frequency higher order filter and thus a lot of phase shift. The simple way is one really slow stage and the rest should be fast - this may even mean using faster OPs than the OPA277.

So one would need an equivalent to the C3 / R4 part of the constant current control loop.

There are at least two options to do that:
1) have a separate R/C combination similar to C3/R4. This could be for example by reusing C3 as well and have a resistor between U4A-output and U1A-input.

2) Use the current control loop as a kind of fast inner loop. This could be done by using U4A as an PI-regulator: add a cap in series to R9 and the power-setpoint to the inv. input. The output of U4A would than work as the set current.  In this case it would be necessary to make C3 considerably smaller to get a much faster current control (e.g. more like 100 pF-1nF for C3).

Power control could be difficult with some sources. One might need to adjust the gain, depending on the load / set-point. As the regulation is nonlinear this is not an easy problem. If might be a good idea to try it in a simulation first. One might need a different solution to make it work with complex power sources over a large range - this could mean making the roll of frequency dependent on the voltage range.

Already for current control there should be an RC snubber at the output. So something like 10 Ohms and 1 µF in series.

Kleinstein, I think I understand most of what you were saying, I'll start off first by saying that I did attempt to simulate this before building it.  I used Multisim, however I must have done something wrong as I didn't see any issues with oscillation or phase shifting in the simulation. I think my best bet may actually be trying to recreate and then fix the oscillation in simulation before I go back to the breadboard.  I'm confused by what you mean when you say use U4A as a "fast inner loop"  would that be some kind of constant feedback that exists in both CI and CP modes?  I'm a bit unsure of what that would do, would that serve to filter any oscillation before it makes it back to the main opamp? Thank you for the reply!

Well, if you don't need the response speed, try switching the OPA2277A with an OP07, shrink R2 to 27 ohm series resistor and get rid of C3.  I've done something similar around 20 years ago, though it was a class A audio amp, the higher speed OP27GP I used at the time also oscillated.  The slower OP07, at the time, with their spec in the data sheet which said 'Guaranteed not to oscillate under large loop delay' did work, but, my full scale audio bandwidth was only around 10Khz.

BrianHG, that actually seems like the most elegant solution if it were to solve the problem.  Since this is working entirely in DC, and is intended for use with DC supplies like batteries or power supplies, speed isn't really of a concern to me.  Theoretically a slow enough opamp would make it impossible for  any oscillation of this frequency to even exist in the circuit.  Am I correct in thinking that?  thank you!

For a first simulation one can use the universal OP model and set the GBW / slew rate accordingly.

There is a principle problem with this simulation: it assumes a kind of low Z source, so that more current means higher power. One you are below a certain voltage, the power vs current curve turns the other way. With just a voltage source with output resistor this is at half the voltage. So regulation will not work for higher current - if will just run to a maximum current.

It would likely be a good idea to have an adjustable current limit also in place, so that the either the power or the current sets the limit, with automatic change over between constant current and constant power. This would be similar to a lab supply with CC and CV modes.
I've actual thought about having a maximum current limit, which is why I placed in D1 to limit the gate voltage of the FET.  Though this wouldn't be adjustable like you said.  I couldn't actually think of an easy way to limit the current in CP mode without directly limiting the gate voltage.  Though I understand what you mean, with something like an AA cell as soon as the voltage drops off this thing will attempt to draw whatever the maximum is set to. Shorting the cell.  I don't know of a solution to this, it almost sounds like I should actually be modulating power by modulating current,  in a way.  I'm curious now, If i were to build the simple constant current load, and include all the requisite filtering to make it stable, I could have another feedback controlled section of the circuit simply control the I set-point.  then by varying that maximum set-point I'm able to vary the maximum current of the system. Since that set-point would now be linearly related to the maximum current I could use an adjustable zener device and allow the user to pick the maximum current they would like.

With my current design, limiting the maximum current by limiting gate voltage required knowing what Vgs is and various parameters of the particular FET.

I will attempt to draw what I am saying and post it so it can be better understood.

#### junits15

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##### Re: FET on opamp output, how to remove oscilations?
« Reply #11 on: December 23, 2016, 10:01:46 pm »
Here is my idea:

If I use the constant current load as the "inner loop" I don't have to do much work to make sure that never oscillates.  I can use what I already have to make sure that is rock solid no matter what.  Then I simply control what that CI load is set to with another opamp with a power feedback loop much like what I already have.  When I want to switch to constant current mode, I simply switch the voltage sense of the power measurement to a precise 1V source.  in that case power equal current so the power feedback amp thenbecomes in essence a current feedback amp.

I can then add something like an LM431 to between the two blocks shown above to pick the maximum current setting, this will be active in both constant current and constant power modes.

#### BrianHG

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##### Re: FET on opamp output, how to remove oscilations?
« Reply #12 on: December 23, 2016, 11:37:10 pm »
Just a quick shot here: have you considered going bipolar for your transistor.  Just adjusting the series resistance coming out of your opamp gives you an additional bit of control on how the current ramps up on your load VS the output voltage of the op-amp.  It will prevent the for-mentioned action of the MOSFET's initial switch jolting on as the gate voltage rises.  Choosing the appropriate series resistance will also create protective current limit for for your system.

Note, You might need an additional small signal transistor emitter-follower at the output of the opamp to boost it's output current.
« Last Edit: December 24, 2016, 12:00:47 am by BrianHG »
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#### evb149

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##### Re: FET on opamp output, how to remove oscilations?
« Reply #13 on: December 24, 2016, 12:18:06 am »
Not there there's any problem with wanting to implement this in analog (obviously it leads to a lot of interesting tinkering and tuning to do so), but if you're just interested in throwing something together to accomplish the result then you might consider using a MCU with ADC/DAC units and make the control loop a digital one.
You could easily update at MHz rates if you wanted to do that with commodity MCUs and probably at 10s of MHz if you wanted to select for a faster ADC and MCU.

The TI C2000 piccolo and other series, for instance (and the dsPIC et. al.) are optimized for this kind of DSP mixed signal control loop processing for applications like motor control and digital power applications (digital SMPS control).

The nice thing about that, of course, is that just a couple lines of code get you things like filtering, ramping, PID, parameter estimation, multiplying, etc. al. which with analog implementations tend to take significant circuit modifications and additions to accomplish.

Probably the best implementations have analog based fault detection / lockout for fast events (over current into a short circuit, reverse polarity input protection or whatever) and digital based control and protection loops for slower V/I ramps, temperature monitoring & control, etc.

#### BrianHG

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##### Re: FET on opamp output, how to remove oscilations?
« Reply #14 on: December 24, 2016, 01:51:01 am »
The TI C2000 piccolo and other series, for instance (and the dsPIC et. al.) are optimized for this kind of DSP mixed signal control loop processing for applications like motor control and digital power applications (digital SMPS control).

Taking things this far, you may as well use the PWM output of the MPU with a gate-driver for the mosfet, add the appropriate inductor and cap on the drain & operate the circuit as a switching circuit.  You'll have a fraction of the heat being radiated in the mosfet due to the current linear semi-switched on operation in the current circuit.  You could use a smaller mosfet as well.  However, you better believe that the mosfet will oscillate!
« Last Edit: December 24, 2016, 01:53:39 am by BrianHG »
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#### orolo

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##### Re: FET on opamp output, how to remove oscilations?
« Reply #15 on: December 24, 2016, 07:04:25 am »
In the osc traces the gate oscillation seems to go between full conduction and cutoff. Could you post a trace of the sense resistor voltage? And, what kind of source are you using with this circuit, is it current-limiting, and what's its resistance? Though improbable, you should discard any chances that oscillation comes from any interaction between your circuit and nonlinearities in the source (like the circuit demanding too much current, the source shutting off, and the cycle repeating again).

#### Kleinstein

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##### Re: FET on opamp output, how to remove oscilations?
« Reply #16 on: December 24, 2016, 10:16:23 am »
Using the current control as an inner loop does not per se prevent oscillations, but it can make things a little easier. This is especially true as no fast control is needed. The system with an inner loop works best if the inner loop is much faster than the outer one. So the current control loop should not be excessively slow (e.g. C3 should be smaller, more like 1-10 nF).

The outer loop for power might still need compensation to make it a controlled fall off to high frequencies, at least if high accuracy is needed. The point is that usually the outer loop should be slower than the inner one.

One could limit the output current with an precision clamp circuit at the input of the current control loop.

#### 2N3055

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##### Re: FET on opamp output, how to remove oscilations?
« Reply #17 on: December 24, 2016, 10:42:44 am »
What I saw in similar schematics, is that usually you don't break or change current feedback loop, but apply power feedback instead current reference voltage from pot.. It might be easier to compensate that way..

#### junits15

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##### Re: FET on opamp output, how to remove oscilations?
« Reply #18 on: December 24, 2016, 08:31:51 pm »
Just a quick shot here: have you considered going bipolar for your transistor.  Just adjusting the series resistance coming out of your opamp gives you an additional bit of control on how the current ramps up on your load VS the output voltage of the op-amp.  It will prevent the for-mentioned action of the MOSFET's initial switch jolting on as the gate voltage rises.  Choosing the appropriate series resistance will also create protective current limit for for your system.

Note, You might need an additional small signal transistor emitter-follower at the output of the opamp to boost it's output current.

I have considered using a bjt, the reason I shyed away is the need for high side current sense when doing power measurements.  Though I'm starting to think that might be easier than trying to make this work with a FET.

#### junits15

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##### Re: FET on opamp output, how to remove oscilations?
« Reply #19 on: December 24, 2016, 08:34:30 pm »
Using the current control as an inner loop does not per se prevent oscillations, but it can make things a little easier. This is especially true as no fast control is needed. The system with an inner loop works best if the inner loop is much faster than the outer one. So the current control loop should not be excessively slow (e.g. C3 should be smaller, more like 1-10 nF).

The outer loop for power might still need compensation to make it a controlled fall off to high frequencies, at least if high accuracy is needed. The point is that usually the outer loop should be slower than the inner one.

One could limit the output current with an precision clamp circuit at the input of the current control loop.

I think this is the best idea, why does having a fast inner loop prevent oscillations?

#### junits15

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##### Re: FET on opamp output, how to remove oscilations?
« Reply #20 on: December 24, 2016, 08:37:29 pm »
What I saw in similar schematics, is that usually you don't break or change current feedback loop, but apply power feedback instead current reference voltage from pot.. It might be easier to compensate that way..
I think this is what I will end up doing, it appears that it will be much simpler to smooth out that way.

#### junits15

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##### Re: FET on opamp output, how to remove oscilations?
« Reply #21 on: December 24, 2016, 09:22:17 pm »
Not there there's any problem with wanting to implement this in analog (obviously it leads to a lot of interesting tinkering and tuning to do so), but if you're just interested in throwing something together to accomplish the result then you might consider using a MCU with ADC/DAC units and make the control loop a digital one.
You could easily update at MHz rates if you wanted to do that with commodity MCUs and probably at 10s of MHz if you wanted to select for a faster ADC and MCU.

The TI C2000 piccolo and other series, for instance (and the dsPIC et. al.) are optimized for this kind of DSP mixed signal control loop processing for applications like motor control and digital power applications (digital SMPS control).

The nice thing about that, of course, is that just a couple lines of code get you things like filtering, ramping, PID, parameter estimation, multiplying, etc. al. which with analog implementations tend to take significant circuit modifications and additions to accomplish.

Probably the best implementations have analog based fault detection / lockout for fast events (over current into a short circuit, reverse polarity input protection or whatever) and digital based control and protection loops for slower V/I ramps, temperature monitoring & control, etc.

Honestly the reason I'm doing this in analog is because I'm not very well versed in using a microcontroller. I've never programmed in assembly for anything before, so I'd be limited to using an Arduino. At that point is rather use analog than wrestle with what I feel are clunky libraries made by people who might not have my use case in mind.  I do think this would be easier and far more precise when done digitally, Im just not able to do that right now.

That isn't to say I couldn't use the project as a learning experience for using an MCU with low level programming, that is one of my future goals for this.  I feel that for now, I can have a lot of fun making this in analog, and after I've taken more university courses I can have fun making this again digitally.

#### BrianHG

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##### Re: FET on opamp output, how to remove oscilations?
« Reply #22 on: December 24, 2016, 09:42:04 pm »
learning experience for using an MCU with low level programming,

This would be programmed in C.  Even an 8 bit PIC at 32 MHz in C would be fast enough, but since the DSPics as just so cheap today, you would use one of them.  It's setting up all the controls for their bloody peripherals which annoys me the most because of poor documentation.

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#### Kleinstein

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##### Re: FET on opamp output, how to remove oscilations?
« Reply #23 on: December 25, 2016, 06:42:12 pm »
Using the (fast) current control loop will compensate for nonlinearity and delays of the FET in the range where the current loop can follow. So up to this frequency this circuit part get very predictable. To get a larger well predictable range it makes sense to have the current loop relatively fast - at least it does not make sense to make the current loop extra slow. Usually it should be no problem to reduce C3 to something like 10 nF and even 1 nF could work.  In any case you need the output snubber - also with a 100 nF cap.

The power control loop could turn out relatively slow anyway. This is because loop gain will depend on the source voltage - so with a 1 V source only, the speed will be only 1/20 of a 20 V source, that still has to be slow enough to get stable.

#### junits15

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##### Re: FET on opamp output, how to remove oscilations?
« Reply #24 on: December 26, 2016, 06:56:08 pm »
learning experience for using an MCU with low level programming,

This would be programmed in C.  Even an 8 bit PIC at 32 MHz in C would be fast enough, but since the DSPics as just so cheap today, you would use one of them.  It's setting up all the controls for their bloody peripherals which annoys me the most because of poor documentation.

Oh ok, so I think this proves how little I know about using a microcontroller.  I wasn't aware there was any way to program a small cheap micro outside of an Arduino with anything other than assembly.   This will be something I will be looking into for sure! Thank you for that suggestion!  I think for now I will stick with finishing this iteration in analog.  Only because I'm fairly close to having this right, to start again in digital would require me to learn the entire process required to get an MCU up and running and then programmed accordingly. Thank you!

In the osc traces the gate oscillation seems to go between full conduction and cutoff. Could you post a trace of the sense resistor voltage? And, what kind of source are you using with this circuit, is it current-limiting, and what's its resistance? Though improbable, you should discard any chances that oscillation comes from any interaction between your circuit and nonlinearities in the source (like the circuit demanding too much current, the source shutting off, and the cycle repeating again).

I was thinking about my source too, so I tried two.  I originally did testing with a computer PSU converted to a bench-top supply.  But I also tested with a seal lead-acid battery and got the same exact results.  Unfortunately I don't have the circuit in the same sate as when I took the first capture, though I will be rebuilding it again and I'll upload a capture then.  From what I remember the current sense oscillation appeared to be in phase with the oscillation on the gate.  Signal shape was similar and frequency was the same,  obviously the magnitude was different.

Using the (fast) current control loop will compensate for nonlinearity and delays of the FET in the range where the current loop can follow. So up to this frequency this circuit part get very predictable. To get a larger well predictable range it makes sense to have the current loop relatively fast - at least it does not make sense to make the current loop extra slow. Usually it should be no problem to reduce C3 to something like 10 nF and even 1 nF could work.  In any case you need the output snubber - also with a 100 nF cap.

The power control loop could turn out relatively slow anyway. This is because loop gain will depend on the source voltage - so with a 1 V source only, the speed will be only 1/20 of a 20 V source, that still has to be slow enough to get stable.

I think this will help, I've been simulating in Multisim and with 1nF and the same 10k resistor the unit takes ~120us to stabilize. vs 1-2ms with the .1uF cap I already have in there.
« Last Edit: December 26, 2016, 07:00:48 pm by junits15 »

#### junits15

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##### yes!
« Reply #25 on: December 27, 2016, 04:01:42 am »
I have solved the Oscillation!
Will post simulation pics later tonight!

#### junits15

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##### Re: FET on opamp output, how to remove oscilations?
« Reply #26 on: December 27, 2016, 04:30:57 am »
The attached .PDF is the new and improved schematic!

The three op amps on the bottom form the current limiter circuit, its basically just a precision clipper with an adjustable upper clipping point and a lower clipping point at 0V. This serves to limit the maximum current of the system to anything up to 10A.  Much more elegan than my previous Zener diode solution.

The "fast inner loop" is the current loop, and I formed the slow outer loop with the AD633, three op amps U1A, U3A, and U3B.  U4A has the power/current setpoint pot on it and feedback from the calculated power out of U3B.  I was noticing a lot of noise at first like you see below:

I then added C1 and R10 and now I get a nice smooth output like this:

With a pulsed input you see the same results, thought made a bit worse when the input switches.  I realize that the trick to getting these oscilations to appear was to use the step input voltage, so that the massive voltage spike when the source turns on would trigger the oscillations.  Using a pure DC source to power the load in simulation results in no osculations oddly enough. I still need to redo the drawing and make sure everything has a footprint associated with it but for now I think the core circuit is complete.  I will also be adding a precision 1V reference, R3 will be switched between the input voltage and the precision 1V reference.  With a 1V input power = current so the power feedback control loop will then function as a current feedback based control loop.

Thank you everyone who offered advice! I really appreciate it!

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