Hi all!
I've been working on a project lately and I've run into a roadblock that I'm not really sure how to get around. To give some backstory, I came across the simple constant current load design floating around using an op amp and a FET with current feedback, like the circuit shown below.
I thought it would be fun to make this into a constant power load, so I used an AD633 analog multiplier IC to measure the power and create power feedback. My circuit is shown below:
The theory is this:
input voltage is measured and divided by 10, input current is measured divided by 10 and sent inverted into the AD633. The multiplication is done inside the chip, giving a value that is equal to (P/100).
Before the signal is sent out of the 633 its divided by 10 again to give (P/1000)
This is then multiplied by 10 and divided by 2 to give (P/200), which swings from 0 to .6. With .6V corresponding to 120W being dissipated. I've picked 120W as the maximum power setting for the circuit. the reason for dividing by 2 is so that the same potentiometer can be used to set constant power as can be used to set constant current. The current measurement was intended to swing between 0 and .5V (corresponding to a 10A maximum). If the power measurement was not divided by 2 at any point it would swing from 0 to 1.2V. In current mode that would mean a max input current of 24A, which is more than I need for this and would complicate the design.
However the thing oscillates like crazy when in constant power mode. The switch S1 picks weather the device is in constant power or constant current mode, up is CI, down is CP. C3 and R4 were used to remove the oscillation in CI mode, however I didn't pick those values and I'm not sure why that setup works. I saw that it was included in someone else's design and that it would remove the oscillations at the gate. Since I don't understand why this works I'm not able to apply this idea to the CP mode of the circuit. At first I thought it was a simple RC filter, but I'm now beginning to think that all that is happening is that the cap C3 is allowing the oscillation to be fed back to the amp and therefore removed. I'm not sure about that though because when adding a similar fixture to the constant power mode, which basically means always having C3 running between the output and the inverting input the oscillation was still present. The capture below shows the gate voltage when the system is oscillating:
I'm not really sure what to do to proceed, my only though is that I somehow need to filter the output of the opamp so that any oscilation will never make it tot he gate of the FET, but i'm not sure how to do that given that the FET poses a capacitive load to the opamp output. Any help would be really appreciated! This is a project I've been working on and off on for a long time and It's killing me that I've put so much work into it only to have it not work as intended. Thank you in advance!
Also! You may disregard the Zener D1, it only serves to be a rough "maximum current" limit for the device. Essentially just limiting the gate voltage to limit the maximum allowed current in constant power mode.
I'm thinking for the sake of simplicity I should set the maximum power limit to be 100W just to make things simpler for calculations.