EEVblog Electronics Community Forum
Electronics => Beginners => Topic started by: Starlord on May 15, 2015, 03:49:15 am
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I'm trying to replace a buffer used in a power control circuit with a mosfet and I'm confused about something.
The circuit in question is here:
[link removed]
I want to replace the buffer because the buffer's output is not 5V tolerant when it's powered by 3.3V and 3.3V cannot drive the input when it's powered by 5V. I considered using a translator instead, but it's more expensive and seems like overkill just to switch the voltage source.
I found this circuit, in the section "MOSFET (Pass Transistor) Interface" which I think could replace it:
http://www.savagecircuits.com/content.php?85-Mixed-Voltage-Systems-Interfacing-5V-and-3-3V-Devices (http://www.savagecircuits.com/content.php?85-Mixed-Voltage-Systems-Interfacing-5V-and-3-3V-Devices)
It's also seen here:
http://www.hobbytronics.co.uk/mosfet-voltage-level-converter (http://www.hobbytronics.co.uk/mosfet-voltage-level-converter)
http://electronics.stackexchange.com/questions/97889/is-there-any-bidirectional-5v-3-3v-level-shifter (http://electronics.stackexchange.com/questions/97889/is-there-any-bidirectional-5v-3-3v-level-shifter)
I was going to use 100K resistors for the pullups, to reduce power consumption. I assume that won't be an issue since this circuit doesn't need to switch fast.
The question I have however is this... If my microcontroller's pins aren't 5V tolerant, what happens when the FET turns on? Will the microcontroller pin see 5V?
I asked someone else, and they said no, a mosfet is a voltage controlled device, and if the gate is at 3.3V then the source will never see more than 3.3V.
That seemed to make sense, until I considered using a mosfet as a switch:
http://www.electronics-tutorials.ws/transistor/tran_7.html (http://www.electronics-tutorials.ws/transistor/tran_7.html)
Here, an N-FET is used in a configuration which isn't terribly different, yet I can apply 3.3V to the gate and switch a 20V power source, if I have a logic-level FET.
So what gives? Was this person wrong? Were they referring to non-logic level FETs? I'm pretty sure even a generic NFET can connect a 20V power source to the source with 5V at the gate and that that would certainly blow up a 5V microcontroller pin connected to said source.
And most importantly, will what I have planned work? This is the part I intended to use in place of the two FETs, with the 100K pullups I mentioned:
http://www.diodes.com/datasheets/DMC2038LVT.pdf (http://www.diodes.com/datasheets/DMC2038LVT.pdf)
It's a PFET and NFET in a single package with sufficient current carrying capacity and power dissipation for what the PFET's body diode may need to conduct.
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Well, that's all rather confusing...
All you need is a NPN BJT with it's collector tied to the gate of the MOSFET. You can drive the base of the BJT from either 3.3V or 5V through a 10k resistor (value not that critical) for instance.
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1. Why did you specify a BJT instead of a FET?
2. Wouldn't the logic on the USB_HOST_EN pin then need to be reversed from the original circuit? I cannot change the signal the microcontroller will output.
I also still want to understand how that level translation circuit protects the 3.3V side because there's clearly something I don't understand about mosfets if in fact that will protect the microcontroller on the 3.3V side from overvoltage at its pin due to the 5V pull up.
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1. Why did you specify a BJT instead of a FET?
Both works. You just don't have to look for a logic level FET, since a BJT works even with 1V.
2. Wouldn't the logic on the USB_HOST_EN pin then need to be reversed from the original circuit?
Yes, it would. In this case, a second stage is needed.
I also still want to understand how that level translation circuit protects the 3.3V side because there's clearly something I don't understand about mosfets if in fact that will protect the microcontroller on the 3.3V side from overvoltage at its pin due to the 5V pull up.
If you replace the buffer IC3 with a transistor (BJT or MOSFET dosen't matter) you are seperating the two voltage rails. Unless the transistor goes smoky, there is no way for the 5V rail to feed through to the 3.3V rail.
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If you replace the buffer IC3 with a transistor (BJT or MOSFET dosen't matter) you are seperating the two voltage rails. Unless the transistor goes smoky, there is no way for the 5V rail to feed through to the 3.3V rail.
Okay, but that's the bit I don't understand. Nothing I have read about mosfets states that Vds cannot exceed the gate voltage. In fact, the whole point of a logic level mosfet is to allow switching higher voltages with a lower voltage, is it not?
Also when a mosfet is on, it's like a very low value resistor. If I just stuck a resistor between my 5V rail and my uC pin I would destroy it unless the pin had voltage clamping diodes, which it doesn't.
So how can the mosfet prevent 5V from flowing from one side to the other, when it's on?
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Here's a nice tutorial on mosfets:
http://www.electronics-tutorials.ws/transistor/tran_6.html (http://www.electronics-tutorials.ws/transistor/tran_6.html)
Is there anything on that page that supports your claim that 5V will not flow from drain to source when the fet is on, which it will be when the uC pulls the source low? because looking at this graph:
(http://www.electronics-tutorials.ws/transistor/tran37.gif?81223b)
...what I see is that Vds can be as high as it likes so long as the Vgs is high enough to put the mosfet into it's full saturation region.
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May I give a short comment to the above contribution?
For my opinion it is not very helpful because the shown graph is misleading and wrong.
The question concerns the OHMIC region only (and not the saturation region) - and this region is not correctly shown in the graph.
From the graph one could derive that the ohmic resistance is nearly the same for all VGS values (constant slope) - and this is not true.
In reality, it is possible to control the FET resistance over a wide range with different VGS values.
It seems that the producer of this graph has used BJT characteristics - edited with VGS values.
(By the way - the "tutorial" contained in the mentioned link contains many errors and false statements).
See Fig.1 in the following link for a correct FET characteristic:
http://www.diodes.com/datasheets/DMC2038LVT.pdf (http://www.diodes.com/datasheets/DMC2038LVT.pdf)
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The question concerns the OHMIC region only (and not the saturation region) - and this region is not correctly shown in the graph.
The question? You mean my question?
Why does my question concern the OHMIC region only? The FET I'm using is logic level, and Vth is way below the 3.3V which will be applied at the gate when the FET is on and the uC pin is pulling the source low. I would expect the FET to be in full saturation.
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No, the saturation region is when the current through the FET depends on VGS. In this case, you don't want your FET to be operating in the saturation region.
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No, the saturation region is when the current through the FET depends on VGS. In this case, you don't want your FET to be operating in the saturation region.
What if the FET is being used as a switch?
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No, the saturation region is when the current through the FET depends on VGS. In this case, you don't want your FET to be operating in the saturation region.
I don't understand. The gate in this circuit is being pulled well above Vth. So how could it not be operating in the saturation region?
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You're confusing FETs with BJTs.
http://en.wikipedia.org/wiki/MOSFET#Modes_of_operation (http://en.wikipedia.org/wiki/MOSFET#Modes_of_operation)
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You're confusing FETs with BJTs.
http://en.wikipedia.org/wiki/MOSFET#Modes_of_operation (http://en.wikipedia.org/wiki/MOSFET#Modes_of_operation)
In what way am I confusing FETs with BJTs?
Triode mode or linear region (also known as the ohmic mode)
When VGS > Vth and VDS < ( VGS – Vth )
Saturation or active mode
When VGS > Vth and VDS ? ( VGS – Vth )
When the uC pin is pulled down, the source sees 0V, the drain sees 5V, and the gate sees 3.3V.
So, with this NFET:
http://www.diodes.com/datasheets/DMC2038LVT.pdf (http://www.diodes.com/datasheets/DMC2038LVT.pdf)
Vth = 0.4 ... 1V
Vgs = 3.3V - 0V = 3.3V
Vds = 5V - 0V = 5V
Vgs-Vth = 3.3V - 1V = 2.3V
And therefore:
Vgs > Vth and Vds > Vgs-Vth
Which Wikipedia states is saturation or active mode, not ohmic mode.
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from the second link you provided:
When the high side transmits a '1' (5V) the MOSFET source pin is pulled up to 3.3V and the MOSFET is OFF.
... so as soon as the source voltage is pulled up high enough by the conducted voltage from the drain side, VGS is below the threshold and the FET no longer conducts.
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from the second link you provided:
When the high side transmits a '1' (5V) the MOSFET source pin is pulled up to 3.3V and the MOSFET is OFF.
... so as soon as the source voltage is pulled up high enough by the conducted voltage from the drain side, VGS is below the threshold and the FET no longer conducts.
I don't understand.
When the mosfet is on, which it is when the uC's pin is low, the uC's pin is connected through the mosfet directly to the 5V pullup.
And connecting that 5V 100K pullup directly to my uC's pin would destroy it right?
(The pin has no overvoltage clamping diode and is not 5V tolerant.)
So how does having the mosfet between them make a difference, if the mosfet is on?
Even if it's only partially on and has some small resistance, that simply increases that 100K resistance between the pin and the 5V rail slightly.
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from the second link you provided:
When the high side transmits a '1' (5V) the MOSFET source pin is pulled up to 3.3V and the MOSFET is OFF.
... so as soon as the source voltage is pulled up high enough by the conducted voltage from the drain side, VGS is below the threshold and the FET no longer conducts.
I don't understand.
When the mosfet is on, which it is when the uC's pin is low, the uC's pin is connected through the mosfet directly to the 5V pullup.
And connecting that 5V 100K pullup directly to my uC's pin would destroy it right?
(The pin has no overvoltage clamping diode and is not 5V tolerant.)
So how does having the mosfet between them make a difference, if the mosfet is on?
Even if it's only partially on and has some small resistance, that simply increases that 100K resistance between the pin and the 5V rail slightly.
You are aware the gate is insulated.. right?
Also, you should stop asking people questions if they say things like "if the gate is at 3.3V then the source will never see more than 3.3V.".
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The MOSFET is only "on" if the voltage difference between gate and source is above a certain threshold, so if the source pin (the one connected to your uC) is being pulled up by applying a high voltage from the drain side, the voltage difference between gate and source is reduced and thereby effectively turns the MOSFET "off".
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You are aware the gate is insulated.. right?
Yes. But how does that change anything?
Also, you should stop asking people questions if they say things like "if the gate is at 3.3V then the source will never see more than 3.3V.".
I trust that it will probably work the way I want it to, but if I don't ask why it will work then I'll never understand mosfets properly and the next time I go to use one I'll be just as lost.
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The MOSFET is only "on" if the voltage difference between gate and source is above a certain threshold, so if the source pin (the one connected to your uC) is being pulled up by applying a high voltage from the drain side, the voltage difference between gate and source is reduced and thereby effectively turns the MOSFET "off".
You're still not making sense.
The mosfet IS on when the uC pin is low. It HAS to be, because if it isn't then it cannot possibly pull the 5V side low and it would therefore not function as a level shifter.
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Replace the mosfet in this picture with a resistor:
(http://www.savagecircuits.com/attachment.php?attachmentid=295&d=1430452949)
When the uC pin is set low, the mosfet turns on and it becomes a hopefully, very low value resistor.
Now I've got a 5V pullup connected to my 3V microcontroller pin. And everything I know says that will destroy my microcontroller. Even with that 3.3V pullup there pulling the voltage down slightly.
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Also, you should stop asking people questions if they say things like "if the gate is at 3.3V then the source will never see more than 3.3V.".
Also, that statement doesn't make sense.
If that were true, I could not switch a 20V source using logic level mosfet because the gate would never see more than 3-5V.
http://www.electronics-tutorials.ws/transistor/tran_7.html (http://www.electronics-tutorials.ws/transistor/tran_7.html)
(http://www.electronics-tutorials.ws/transistor/tran21.gif?81223b)
uC pin goes high, gate sees 5V, source is connected to 20V source powering lamp. Source sees more than 5V.
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The MOSFET is only "on" if the voltage difference between gate and source is above a certain threshold, so if the source pin (the one connected to your uC) is being pulled up by applying a high voltage from the drain side, the voltage difference between gate and source is reduced and thereby effectively turns the MOSFET "off".
Wait. Perhaps you mean it turns it partially off?
Ie, the 5V side - the drain in this case, pulls the "3.3V" side, ie, the source (and my microcontroller pin) up from 0V to... what? Some voltage where the mosfet's resistance is high enough that some kind of equilibrium is reached? I mean it can't reach 3.3V because that would turn the mosfet "off" and if the mosfet is "off" then it can't pull the 5V side down to 0V to do the level translation.
But at the same time, the 5V side can't pull the source up that much, because if the source isn't at 0V then how could the 5V side be at 0V?
So this equlibrium point would have to be slightly more than 0V but still very close to 0V, wouldn't it? And the mosfet's resistance would have to be much less than the pullup on the 5V side. Because there's a voltage divider formed there between the mosfet's resistance and the voltage at the source and the 5V pullup.
Ugh, none of this is making any sense.
And I tried to simulate this with Digikey's PartSim and I was unable to ever get the voltage on the 5V side below 5V. :(
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Also, you should stop asking people questions if they say things like "if the gate is at 3.3V then the source will never see more than 3.3V.".
Also, that statement doesn't make sense.
It does make sense. The MOSFET will not conduct when VGS is 0V, therefore the source voltage will not be higher than the gate voltage.
If that were true, I could not switch a 20V source using logic level mosfet because the gate would never see more than 3-5V.
The 20V switch is a common source circuit ("low side switch"). The level translator is a common drain circuit. Totally different. In fact, you can't easily use an N MOSFET as a 20V high side switch.
uC pin goes high, gate sees 5V, source is connected to 20V source powering lamp. Source sees more than 5V.
Now this does not make sense. In the 20V switch circuit, the source is grounded.
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Perhaps you could explain in a little more detail what you're doing. What micro, what type of FET you have selected, etc..
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It does make sense. The MOSFET will not conduct when VGS is 0V, therefore the source voltage will not be higher than the gate voltage.
Obviously there is some critical concept here I'm having a hard time grasping.
Let's say I have a 5V power source, a resistor, and my 3V microcontroller pin. If I connect the 5V source to the resistor and then the resistor to my microcontroller, I will destroy the microcontroller.
Now I do the same with a mosfet in the resistor's place. What's changed?
We know the mosfet must be on and in a low resistance state, because otherwise the microcontroller could not pull the 5V side down when it's pin goes LOW. The mosfet's resistance and the pullup form a voltage divider, and the drain pin is the point between them we tap and connect to he PFET. For that point to be near 0V, the mosfet MUST be almost fully on, with a resistance of less than a few ohms.
And if the mosfet is almost fully on, then that means there's almost no resistance between that 5V pullup and the uC pin. Which is the same as my example with just the resistor. And the uC will be destroyed.
Except you say it won't. That the source can never go above the gate. That's fine, and I'd accept that, except it directly conflicts which what I just said about how the mosfet's resistance must be low, and therefore effectively a dead short between my uC pin and that 5V pullup... which would destroy the pin.
What am I missing here?
If that were true, I could not switch a 20V source using logic level mosfet because the gate would never see more than 3-5V.
The 20V switch is a common source circuit ("low side switch"). The level translator is a common drain circuit. Totally different. In fact, you can't easily use an N MOSFET as a 20V high side switch.
I don't understand the difference. If I took that drawing and put my uC pin where the ground is, and set it low, it would look very much the same, and would the lamp not still light when 3.3V is applied at the gate? That is, until the pin burnt out.
uC pin goes high, gate sees 5V, source is connected to 20V source powering lamp. Source sees more than 5V.
Now this does not make sense. In the 20V switch circuit, the source is grounded.
And it is grounded when I set my uC pin low as well, is it not?
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Perhaps you could explain in a little more detail what you're doing. What micro, what type of FET you have selected, etc..
All the details are in the first post. It's a microcontroller which doesn't have 5V tolerant inputs, and the circuit is for selecting between VIN or USB power, with support for USB OTG where the uC may need to manually override the ID pin and connect VIN to the USB bus. The original circuit used a PFET and buffer. But I believe the original schematic is in error because the buffer selected does not have 5V tolerant outputs when powered with 3.3V, as it is. As such I believe the 5V pullup will eventually destroy it. I considered replacing it with a translator with dual supplies and therefore 5V tolerant outputs, but it's twice as expensive, and it seems crazy to use that when for slightly more than a single PFET I could use a part like this:
http://www.diodes.com/datasheets/DMC2038LVT.pdf (http://www.diodes.com/datasheets/DMC2038LVT.pdf)
Which has a PFET and NEFT and costs only slightly more than the PFET alone.
Plus, I'm a stubborn asshole and I want to understand how to use mosfets properly. A few cents savings be damned.
(Also for the purposes of this exercise I can't invert the logic on the uC's pin, so I can't use the NFET in a normal low-side configuration.)
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All the details are in the first post. It's a microcontroller which doesn't have 5V tolerant inputs
What microcontroller? You say it doesn't have 5V tolerant inputs, I say it's likely it can sink 17uA.. so, what microcontroller?
The original circuit used a PFET and buffer. But I believe the original schematic is in error because the buffer selected does not have 5V tolerant outputs when powered with 3.3V, as it is. As such I believe the 5V pullup will eventually destroy it.
I believe otherwise, but you may have difficulties depending on the FET.. which is why I asked what FET.
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is it the concept of Vgs that's bothering you?
If the uC pin goes to 0V then you have 3.3V across the resistor R1 that goes between the MOSFETs Gate & Source, which means Vgs = 3.3V, MOSFET conducts. this means that the MOSFET then SINKS the 5V side to 0V too through the uC pin that is at 0V.
Imagine that this circuit where the 3.3V signal is grounded
(http://www.savagecircuits.com/attachment.php?attachmentid=295&d=1430452949)
its a similar thing, the uC is not seeing the 5V signal when in this situation. The point at 5V signal will be 0V from the uC IO.
And vice versa. when uC IO goes 3.3V again, the voltage across R1 (Vgs) is = 3.3V(uC) - 3.3V(pull up supply) = 0V - no conduction, no current flow through FET, 5V signal is allowed to float to 5V by pull up R2.
I hope I made it clearer?
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We know the mosfet must be on and in a low resistance state, because otherwise the microcontroller could not pull the 5V side down when it's pin goes LOW. The mosfet's resistance and the pullup form a voltage divider, and the drain pin is the point between them we tap and connect to he PFET. For that point to be near 0V, the mosfet MUST be almost fully on, with a resistance of less than a few ohms.
I'm commenting on the BS170 circuit shown a few posts up, which is a standard level shifter.
The MOSFET is not like a resistor. As the source voltage rises, VGS drops and the resistance increases; it is approximately infinite at VGS = 0.
Going back to the original circuit, I think that the 74LVC1G125 output is 5V tolerant in the off state, although that's not specified in the datasheet.
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All the details are in the first post. It's a microcontroller which doesn't have 5V tolerant inputs
What microcontroller? You say it doesn't have 5V tolerant inputs, I say it's likely it can sink 17uA.. so, what microcontroller?
It can sink quite a bit more than 17uA, but the pins are still rated for only 3.3V and I see no mention of clamping diodes:
http://www.atmel.com/Images/Atmel-42181-SAM-D21_Datasheet.pdf (http://www.atmel.com/Images/Atmel-42181-SAM-D21_Datasheet.pdf)
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It will have clamping diodes.
More to the point, you don't even need them. Pull the FET up to +3.3V (forget the buffer). Use a pFET with a threshold of -2V or worse, which turns on acceptably at -4.5Vgs. No buffer, no current flowing through protective diodes.
Use a current limiting resistor on the gate.
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Pull the pFET up t 3.3V?
That's one of the first solutions I considered. I was told when I asked here in another thread about this that I couldn't do that. That the FET wouldn't turn on fully.
https://www.eevblog.com/forum/projects/usb-power-supply-selector/msg672644/#msg672644 (https://www.eevblog.com/forum/projects/usb-power-supply-selector/msg672644/#msg672644)
You can not use you MCU pin, unless it supports open drain output, because 5V-3.3V=1.7V, many fets will conduct at Vgs=-1.7V.
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Which is why I said to pick one with a threshold of -2V. Yes, they exist, I went looking earlier and found hundreds.
E: Take a look at, say, this one: http://www.digikey.com/product-detail/en/AO4425/785-1026-1-ND/1855968 (http://www.digikey.com/product-detail/en/AO4425/785-1026-1-ND/1855968)
Vgs minimum -2V, max -3V, theoretically <50mOhm at -4.5V. Simple enough to test. No 5V pullup needed.
For more headroom, 100k pullup to 5V, 10k series between pin and gate. Minimum leakage current, -1.3Vgs or so when high.
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Replace the mosfet in this picture with a resistor:
(http://www.savagecircuits.com/attachment.php?attachmentid=295&d=1430452949)
When the uC pin is set low, the mosfet turns on and it becomes a hopefully, very low value resistor.
Now I've got a 5V pullup connected to my 3V microcontroller pin. And everything I know says that will destroy my microcontroller. Even with that 3.3V pullup there pulling the voltage down slightly.
Let's go with your analogy of the MOSFET being a low value resistor )let's say 0.1 Ohm). In this case we can forget the gate altogether and the pull-up to 3.3 as well. Setting the uC pin low would be equivalent with connecting it to ground via a fairly low resistor (lets say 50 Ohm). So you have:
GND -- [ 50 Ohm] --- uC-pin --- [MOSFET, 0.1 Ohm] --- [4.7kOhm] --- 5V
This is a classic voltage divider circuit, with the voltage at the uC pin being much much closer to GND (approx. 10mV) than to 5V (or 3.3V if you include the other pull-up as well).
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Which is why I said to pick one with a threshold of -2V. Yes, they exist, I went looking earlier and found hundreds.
That's great, but "You can not use you MCU pin, unless it supports open drain output," seems pretty cut and dry. I assumed if they said I cannot use my MCU pin it meant there was some other issue with using one with a lower threshold that I didn't understand.
And did you not just say:
Also, you should stop asking people questions if they say things like "if the gate is at 3.3V then the source will never see more than 3.3V.".
He said it wouldn't work, I stopped asking questions about it. :)
For more headroom, 100k pullup to 5V, 10k series between pin and gate. Minimum leakage current, -1.3Vgs or so when high.
Huh?
http://www.savagecircuits.com/content.php?85-Mixed-Voltage-Systems-Interfacing-5V-and-3-3V-Devices (http://www.savagecircuits.com/content.php?85-Mixed-Voltage-Systems-Interfacing-5V-and-3-3V-Devices)
Series Resistor Interface
A series resistor is sometimes used to interface 5V/3.3V devices, however it is important to understand that not all devices can be connected in this manner. This type of interface requires the 3.3V device to have protection from over-voltage on the I/O pins. This is done using clamping diodes which are designed to limit the input voltage to ~3.3V. These clamping diodes are pretty robust, however they are not meant to continuously sink large amounts of current. The series resistor limits the current across the clamping diode so that it is not permanently damaged.
Figure 2 shows a series resistor interfacing 5V and 3.3V devices. The value of R1 is based on the current capability of the clamping diodes.
(http://www.savagecircuits.com/attachment.php?attachmentid=288&d=1430452949)
Not all 3.3V devices are able to be connected in this manner. If your device does not include clamping diodes you should not use a series resistor to interface to the 5V signal. While the 3.3V device may appear to function, it will eventually fail from electrical stress.
Is a 5V pullup with 100K and 10K resistors between it and my pin not a series resistor interface?
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GND -- [ 50 Ohm] --- uC-pin --- [MOSFET, 0.1 Ohm] --- [4.7kOhm] --- 5V
This is a classic voltage divider circuit, with the voltage at the uC pin being much much closer to GND (approx. 10mV) than to 5V (or 3.3V if you include the other pull-up as well).
Huh? So I DON'T need clamping diodes, or a level shifter, or a voltage divider on a 3V microcontroller pin if I want to read 5V logic? All I need is a resistor, and that's fine?
I've spent all week on this problem and read so many web pages about level shifting methods and I haven't seen any mention of a simple resistor being good enough UNLESS there were also clamping diodes on the pins.
I thought sinking 5V to a 3.3V micrcontroller, even through a current limiting resistor was bad unless it's pins were 5V tolerant. :/
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And what makes you certain you don't have clamp diodes?
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And what makes you certain you don't have clamp diodes?
Because I haven't seen any mention of them in the datasheet and haven't found any diagram of the port with them in place, and the datasheet specifies 3.6V as the absolute max?
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And what makes you certain you don't have clamp diodes?
Because I haven't seen any mention of them in the datasheet and haven't found any diagram of the port with them in place, and the datasheet specifies 3.6V as the absolute max?
No, it specifies 3.8V max for Vdd, and pin voltage as GND -0.3V to Vdd +0.3V.
Try a test. Take a nice high value resistor, and connect a GPIO pin to +5V with it. Drive the GPIO high. Check the voltage on the pin.
If it's not ~350mV above Vdd and being clamped, you win.
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No, it specifies 3.8V max for Vdd, and pin voltage as GND -0.3V to Vdd +0.3V.
But I'm not supplying Vdd with 3.8V, I'm supplying it with 3.3V. So the absolute max for the pin is 3.6V.
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No, it specifies 3.8V max for Vdd, and pin voltage as GND -0.3V to Vdd +0.3V.
But I'm not supplying Vdd with 3.8V, I'm supplying it with 3.3V. So the absolute max for the pin is 3.6V.
Yes, I can do simple addition too.
Ask yourself what happens beyond that point. You're still below the absolute max for the chip, so why is the max input voltage always +/- 0.3V? Because there are diodes clamping to the rails.
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Yes, I can do simple addition too.
Ask yourself what happens beyond that point. You're still below the absolute max for the chip, so why is the max input voltage always +/- 0.3V? Because there are diodes clamping to the rails.
I can ask myself what happens till the cows come home and it won't do any good because I don't know anything about what the limitations of the silicon are or why those limits exist or are different from chip to chip.
Why's the limit +-0.3V? You want me to guess? I would have guessed it's to prevent current from flowing somewhere it shouldn't because it's too high relative to Vcc. But that doesn't mean it's caused or limited by clamping diodes. Also, if there were clamping diodes and the pins were 5V tolerant, you'd think Atmel would advertise that since it would sell more chips. But I can't find a single mention of diodes or 5V tolerance in the datasheet.
Furthermore, without any actual electrical specs, I don't know how much current said diodes can actually sink, so I can't count on them. You said I should try it and see if it works. But you seem to be a smart fellow who knows more about this than I do. So why is it you're suggesting that when you know it's possible to exceed a rating without immediately destroying a chip, only to have it fail later for unknown reasons? This isn't some one off project, this is a microcontroller circuit I'm going to use in lots of things I build. I don't want to have random failures happening that I can't trace the cause of.
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Also, if there were clamping diodes and the pins were 5V tolerant, you'd think Atmel would advertise that since it would sell more chips.
They're not 5V tolerant, if they were you wouldn't need to limit the current with a resistor for the diodes to safely clamp..
Furthermore, without any actual electrical specs, I don't know how much current said diodes can actually sink, so I can't count on them. You said I should try it and see if it works.
We are talking a few tens of microamps. The diodes should handle that without a problem.
But you seem to be a smart fellow who knows more about this than I do. So why is it you're suggesting that when you know it's possible to exceed a rating without immediately destroying a chip, only to have it fail later for unknown reasons? This isn't some one off project, this is a microcontroller circuit I'm going to use in lots of things I build. I don't want to have random failures happening that I can't trace the cause of.
Then let's wait for someone else to come along and say a few microamps of current won't cause harm.
You could also ask Atmel to clarify their incomplete datasheets.
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http://www.avrfreaks.net/forum/input-protection-diodes-atmel-port-pins (http://www.avrfreaks.net/forum/input-protection-diodes-atmel-port-pins)
Taking the side of evil here:
If you put a 1M resistor between the port pin and the 9v input, the protection diode will conduct less than 9uA and keep the input pin from going above VCC+0.5v.
Not sure I'd do it for anything I wanted to put in customer's hands.
The Lawson is spot on,you should get more respect for operating the uC within its specification.There is nothing wrong with modifying the design and its OK to make mistakes as we learn from these.You dont want to apply 9V directly to the I/O pins even through a resistor. The protection diodes are unlikely to respond quick enough to prevent the i/o circuitry seeing out-of spec voltage.
This is why I have trust issues.
Well, that and spending a week trying to find an alternative solution after someone told me I could not drive my PFET with a 3.3V uC pin. :(
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The question concerns the OHMIC region only (and not the saturation region) - and this region is not correctly shown in the graph.
The question? You mean my question?
Why does my question concern the OHMIC region only? The FET I'm using is logic level, and Vth is way below the 3.3V which will be applied at the gate when the FET is on and the uC pin is pulling the source low. I would expect the FET to be in full saturation.
Sorry for my late answer - yes, starlord you are right. I did read "voltage controlled resistor" instead of "... devices". Sorry.
Nevertheless, my comment is valid: The shown input-output characteristics do NOT belong to a FET but to a bipolar transistor.
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Well, crap. I've just been going over the circuit again and I found a problem.
When Vin is powered, the FET turns off. But this doesn't disconnect Vin from the USB supply entirely - the body diode of the FET can still conduct. And that means the USB port could potentially charge my battery. Which would be bad if the battery voltage is less than the 5V USB supply, which it will most likely be.
I also can't simply stick a diode on Vin to fix the problem because my voltage regulator has a maximum drop of 250mV, and a schottky has a voltage drop of around 350-500mV. So if I'm powering the circuit with a LiPo, that's 3.7V nominal, and I'm down to 2.95V coming out of my regulator.
I see they did something weird on the SamD21 Xplained Pro board with two PFETs back to back:
http://www.atmel.com/Images/Atmel-42220-SAMD21-Xplained-Pro_User-Guide.pdf (http://www.atmel.com/Images/Atmel-42220-SAMD21-Xplained-Pro_User-Guide.pdf)
http://www.digikey.com/product-detail/en/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500 (http://www.digikey.com/product-detail/en/IRLML6402TRPBF/IRLML6402PBFCT-ND/812500)
But I don't know where to start figuring out how that works.
And they're using these NFETs to invert the logic on the ID pin:
http://www.digikey.com/product-detail/en/2N7002DW/2N7002DWCT-ND/1785790 (http://www.digikey.com/product-detail/en/2N7002DW/2N7002DWCT-ND/1785790)
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It seems to me you've found your circuit.
Back to back pFETs, to get around body diode conduction, pulled to +5V so you don't need to worry about threshold voltage, two nFETs as a level shifter (two stages so the output is not inverted).
Pretty much what the first reply to the thread suggested as far as driving the pFETs.
Low parts count and minimal engineering effort required.
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It seems to me you've found your circuit.
Back to back pFETs, to get around body diode conduction, pulled to +5V so you don't need to worry about threshold voltage, two nFETs as a level shifter (two stages so the output is not inverted).
Pretty much what the first reply to the thread suggested as far as driving the pFETs.
Low parts count and minimal engineering effort required.
Except I don't have a 5V supply on Vin. Vin could be anywhere from 3.5-6.5V.
And I suspect I can't simply pull the FETs up to the USB supply because that will change the behavior of the circuit.
And now I've gone from a circuit that used a buffer and one FET with two pullups to using four FETs and three pullups and I'm sure there's got to be a simpler way of doing this.
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It seems to me you've found your circuit.
Back to back pFETs, to get around body diode conduction, pulled to +5V so you don't need to worry about threshold voltage, two nFETs as a level shifter (two stages so the output is not inverted).
Pretty much what the first reply to the thread suggested as far as driving the pFETs.
Low parts count and minimal engineering effort required.
Except I don't have a 5V supply on Vin. Vin could be anywhere from 3.5-6.5V.
Which only matters if you try and connect a USB host to the port with Vin too low. In which case, well.. I suggest you shouldn't do so. Alternatively we could go back to the high threshold FETs.
And now I've gone from a circuit that used a buffer and one FET with two pullups to using four FETs and three pullups and I'm sure there's got to be a simpler way of doing this.
This IS the simple way. It is a bog standard every day circuit. The parts are cheap, small, and common. Good grief, don't look inside an IC if you think this isn't simple.
I am beginning to think you may need a dentist.
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Which only matters if you try and connect a USB host to the port with Vin too low. In which case, well.. I suggest you shouldn't do so. Alternatively we could go back to the high threshold FETs.
Don't you mean low threshold FETs?
It's confusing using terms like high and low when talking about negative voltages. Do you mean fets with a Vth of < -4.5V? Or < -2V?
Either way, I think I found a problem with the earlier circuit when using FETs that have too negative a threshold voltage. For example, if Vin is only 3.6V, and I pull the gate down to enable USB OTG, Vgs will only reach -3.6V, so a Vth of -4.5V won't work.
This IS the simple way. It is a bog standard every day circuit. The parts are cheap, small, and common. Good grief, don't look inside an IC if you think this isn't simple.
And yet, we've seen it's possible to make a non-inverting level shifter using a single FET, but this circuit uses two.
Using four transistors where only two would suffice is bad design. If only because it wastes precious space on the PCB and increases your BOM and placement costs.
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Which only matters if you try and connect a USB host to the port with Vin too low. In which case, well.. I suggest you shouldn't do so. Alternatively we could go back to the high threshold FETs.
Don't you mean low threshold FETs?
It's confusing using terms like high and low when talking about negative voltages. Do you mean fets with a Vth of < -4.5V? Or < -2V?
Higher magnitude. -2V is a greater magnitude than -1V. -4.5V threshold would never work for 5V switching, let alone lower.
Either way, I think I found a problem with the earlier circuit when using FETs that have too negative a threshold voltage. For example, if Vin is only 3.6V, and I pull the gate down to enable USB OTG, Vgs will only reach -3.6V, so a Vth of -4.5V won't work.
If Vin is only 3.6V and you pull the gate down to enable USB OTG, you'll only have 3.6V going out to a device expecting 5V.
And yet, we've seen it's possible to make a non-inverting level shifter using a single FET, but this circuit uses two.
Using four transistors where only two would suffice is bad design. If only because it wastes precious space on the PCB and increases your BOM and placement costs.
And yet Atmel used it because it's good design: You don't spend a week fussing over it.
There are off-the-shelf power switches which can probably do this with no external components if you really care about that.
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I'm still lost.
I'm trying to figure out how Atmel's circuit works. The one where they've got two PFETs back to back:
USB - DS - SD - VIN
For the sake of argument, let's say I want to ditch the NFETs and pull the gate up to 3.3V instead so I can drive it directly with my uC pin and the ID signal for USB OTG. (ID is connected to ground when VIN should be powering the USB. Otherwise it is not connected.)
And this is what I know about how PFETs work:
If Vgs < Vt and Vgd > Vt, then S and D are connected by a variable resistance.
If Vgs < Vt and Vgd < Vt, the resistance drops to Rds ON.
If Vgs > Vt the FET is off.
So let's say I have 5V on USB and 3.6V at Vin.
USB = 5V
Vin = 3.6V
G of Vin side PFET = 3.3V
G of USB side PFET = 3.3V
But that's as far as I get. The source pins of the PFETs are connected together and, and the body diodes of the PFETs are pointing at each other, so no current should be able to flow. And if no current is flowing, wouldn't that mean the source pin of each PFET has to be at the same potential as its drain pin? But the two are connected together. So they can't be at different potentials or current would flow between them. Which it can't because of the body diodes. UGH.
To make matters worse, this circuit doesn't even seem right. I'm sure it works fine on Atmel's board with the 5V supply and the power multiplexer, but unless I tap it off between the USB and Vin PFETs, I can't see how it could work for my needs. I only just came to this realization now.
If The USB is at 5V and Vin is at 3.6V then I want the USB to supply power to the 3.3V regulator. But I don't want the USB supplying VIN.
I also noticed that in my simplified circuit with a single PFET, the problem I was having with the body diode allowing the USB to power VIN is because the diode is pointing at Vin. But in the Atmel circuit, it's pointing away from Vin. So I guess I need to do some more math and try to figure out if I can, or why I can't just flip that PFET around.
Ugh, this seemingly simple circuit is such a pain in the ass.
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They are not connected source to source. Look again.
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Son of a bitch.
Okay, so two PFETs back to back with their drains connected, and the supply line for my 3.3V regulator connected between them.
If ID or uC is LOW, both the gates of both FETs need to be pulled LOW so they're ON and Vin can supply the USB.
(And yes, I am aware that supplying a USB device with less than 5V is bad, this feature will only be used when Vin is supplied with 5V.)
If USB is HIGH, pull Vin FET gate HIGH to turn it OFF, so USB won't backfeed battery.
Except... USB can be HIGH if it's being fed from Vin. So I can't switch the Vin FET on or off based on the USB voltage level alone.
I guess I need to use the state of the USB FET's gate to set the state of the Vin gate?
Hm...
If USB is LOW, pull Vin FET gate LOW to turn it ON?
Hm... I'm not sure if I'll be able to figure out how to make that work, but if that won't work, I could try reversing things, so if Vin is powered, the USB won't power the circuit, and it's only connected if ID or uC pin is LOW, stating that the USB should be powered from Vin. This might be easier. Plus... if the device requires more than 500mA having Vin be the primary supply would allow the device to be powered properly even when being programmed. (Though that's an unlikely circumstance.)
Also I wish the forum would stop timing out on me while I'm in the middle of typing my replies. :/
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So I'm still having difficulty with this, but I'm making some progress, in figuring out what WON'T work at least.
There's something I don't get about the Atmel schematic though.
The Atmel SamD21 Xplained schematic shows two PFETs, with their drains connected. The body diodes point away from eachother, to the source pin of each FET.
Now here's the thing I don't get:
A PFET is OFF when Vgs > Vth, and for PFETs, Vth can be between 0.4V and 4V depending on the FET.
But the voltage at each source is 5V in that circuit. And the voltage at the gate is 5V at most. That would mean Vgs, at most, would hover around 0V. Which is not enough to ever turn the FET completely off.
Am I wrong?
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I think to solve this I need to connect the mosfets back to back, such that the sources are connected. It appears I can do this with either P or N FETs. I'm not sure what the difference is when using one or the other, aside from the logic at the gate being reversed, but using PFETs seems to be suggested for this kind of circuit far more often than NFETs, which is strange to me because NFETs are cheaper, and tend to be smaller for the same power dissipation rating.
But here's an example of two NFETs connected in this manner:
(http://m.eet.com/media/1054504/TI_ORing_Fig4.gif)
My question is this:
With the sources connected like this, how do I determine what Vgs is? Like, if I set the gate high or low, I can't calculate what Vgs is to determine if it is above or below Vth. With a PFET I can calculate that because the body diode can conduct, but here... well I don't know what's going on inside the FET.
I assume that pulling it high will turn it on, but I don't like assuming. :/ I want to know WHY and when it will turn on.
I mean as far as I can tell the source of both NFETs should be in a hi-z floating state. So the behavior when I set the pin high or low should be unpredictable.
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Ugh, god damnit!
I spent the last two days drawing up circuit diagrams and doing calculations while working on the assumption that P-FET voltage thresholds were always between +0.4V and 4V because when I wanted to know what the range of thresholds were I went to Digikey, searched for PFETs, and looked at the range of values on the chart:
http://www.digikey.com/product-search/en?x=0&y=0&lang=en&site=us&keywords=PMV48XP (http://www.digikey.com/product-search/en?x=0&y=0&lang=en&site=us&keywords=PMV48XP)
BUT THE FRIGGIN VALUES ARE WRONG.
The Vgs on that part isn't 1.25V, it's -1.25V!
I have to assume the same is true for all the rest of the parts.
Also, while I'm ranting, if you don't include the body diode in your diagram of a mosfet in your tutorial on mosfets, I hate you. And if you don't label the gate, source, and drain I hate you a little less, but I still hate you. I also hate you if you just call it a FET and don't mention if it's a PFET or NFET. I've had to keep going back and forth between six different mosfet diagrams just to keep track of what's what. I think I've got most of it memorized now, but my god. It could have been so much easier to learn this if people just took the time to label all the parts. And leaving the body diode out is just unforgivable.
Well, back to the drawing board. I wasn't making much progress on getting this to work, but maybe now that I know the right polarity for the threshold I can figure something out. :/