EEVblog Electronics Community Forum
Electronics => Beginners => Topic started by: JoeN on November 10, 2015, 05:30:18 am
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This is my very first simulation! I posted about this circuit before, it was designed by Hans Camenzind and included in his book Designing Analog Circuits. I wanted to get this going as a discrete circuit. I have a simulation of it that says it should work. The waveform is a little different than Hans has it in his book but close enough for me. My circuit follows his design correctly, I think. I built two of these. Both of them behave the same. When 12V is applied, I get about 9.4V at the output, no periodic waveform. I guess it is up to me to start probing this mother and see where it begins diverting from the simulation, but I would love some pointers. Why, other than obviously screwing up the circuit in some way or assembling it incorrectly (which I am betting against), would a circuit like this one's behavior divert from the simulated results to such a large degree? Is there something obvious that I am missing?
As Hans designed it:
(https://www.eevblog.com/forum/beginners/figuring-out-why-an-actual-circuit-is-not-working-like-the-simulated-circuit/?action=dlattach;attach=181048)
As I drew my schematic in LTSpice. I am using the surface mount version of these transistors and the resistor values are chosen to be standard values:
(https://www.eevblog.com/forum/beginners/figuring-out-why-an-actual-circuit-is-not-working-like-the-simulated-circuit/?action=dlattach;attach=181050)
LTSpice's results at the output terminal:
(https://www.eevblog.com/forum/beginners/figuring-out-why-an-actual-circuit-is-not-working-like-the-simulated-circuit/?action=dlattach;attach=181052)
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For what it's worth, the DipTrace schematic and the PCB
(https://www.eevblog.com/forum/beginners/figuring-out-why-an-actual-circuit-is-not-working-like-the-simulated-circuit/?action=dlattach;attach=181054)
(https://www.eevblog.com/forum/beginners/figuring-out-why-an-actual-circuit-is-not-working-like-the-simulated-circuit/?action=dlattach;attach=181056)
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The first thing you'll need is to sort out power supply decoupling.
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The first thing you'll need is to sort out power supply decoupling.
I can throw a 10uF chip cap across those input terminals. Do you really think it may be that simple?
I'm an idiot. I didn't see an IC. So I didn't think to decouple it (though it is an IC, just without the I). But somehow, I can't believe it will be that simple. Still, thanks for that idea. I will do that first thing.
Edit: Nope, didn't work. But at least I have that "fixed".
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I'm going to assume that there's a solid ground plane on the back side of the board.
You'll need to decouple every point that connects to Vcc.
Then I suspect you'll need a collection of other caps to stop bits oscillating.
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The mirrors are extremely over-the-top. Four transistors (and more) is typical for precision mirrors when you are stuck with lateral PNP (hFE < 10), but 2N3906s outperform them considerably.
Having no emitter resistors (in several places) is also a problem. It should still work, but expect lopsided waveforms, particularly at high current (= thermal imbalance) and low current (= Vbe mismatch).
CML (current mode logic -- starting with a current sink at the bottom, and steering it through diff pairs until it reaches load resistors at the top) is prone to oscillation when tall stacks and long traces get involved. Routing is non-obvious: you want the traces to be high impedance to let the current flow relatively unimpeded, but sooner or later, you need low impedances (e.g., ground plane shielding) to keep things in order. The RF response is that of a series of cascode amplifiers, so expect high sensitivity for the transistors near the bottom (current sinks and first diff pairs). Reduce sensitivity by adding series base resistance (10-100 ohms) or a ferrite bead.
As long as supply current is constant, supply bypass isn't a big deal, but do try to keep current paths nearby. That is, a current path starting with a current sink, should follow as near a common path as possible until it reaches the supply. Each time it splits (i.e., goes through a diff pair), keep those paths close together. That way, when the current paths switch state, the current is drawn from nearly the same location on the supply rail. Imagine hanging from a railing with one hand, then grabbing it with your other hand: you have to move over, but the less you move, the easier it is (and the less the rail will bounce in the process).
Tim
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Oh and I remember specifically noting this in the previous thread:
Q11 has two emitters.
Your LTSpice has one, which is why the falling edge is so slow. In fact, it's almost complete luck that it falls at all. (The only reason it does, is because of base currents.)
Mismatch in your real circuit means it probably won't work at all. Or maybe it will, depending on which transistors are warmer than others.
Use two 2N3904s in parallel.
Tim
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Matched transistors.
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Matched transistors.
I suspect that's the least of the issues, too much gain, both at DC and at RF will both cause grief.
It might be fun to assign different transistors to the spice model to see the effects of unmatched transistors, or possibly just changing some parameters on a random basis across the model, though it is probably better to break it down into different segments to see the effects of mismatch and temperature on a block by block basis.
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I'm going to assume that there's a solid ground plane on the back side of the board.
There is
You'll need to decouple every point that connects to Vcc.
You have to be kidding me, how then does any IC work? ICs don't contain a bunch of internal caps for every transistor and use typically only one for the whole circuit.
Then I suspect you'll need a collection of other caps to stop bits oscillating.
See my last comment.
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The mirrors are extremely over-the-top. Four transistors (and more) is typical for precision mirrors when you are stuck with lateral PNP (hFE < 10), but 2N3906s outperform them considerably.
Having no emitter resistors (in several places) is also a problem. It should still work, but expect lopsided waveforms, particularly at high current (= thermal imbalance) and low current (= Vbe mismatch).
Tell Hans. I assume he knew this was a problem but was being compensated for by matched transistors? Maybe I should simulate PNP transistors with hFE = 10?
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Oh and I remember specifically noting this in the previous thread:
Q11 has two emitters.
Your LTSpice has one, which is why the falling edge is so slow. In fact, it's almost complete luck that it falls at all. (The only reason it does, is because of base currents.)
Mismatch in your real circuit means it probably won't work at all. Or maybe it will, depending on which transistors are warmer than others.
Use two 2N3904s in parallel.
Tim
You mean two transistors with the same nets for all three terminals, right? I could just stack another 2N3904 on top of that one? I can physically pull that off I think and test it with the board I have now. I will add that to the simulation and see what happens.
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The mirrors are extremely over-the-top. Four transistors (and more) is typical for precision mirrors when you are stuck with lateral PNP (hFE < 10), but 2N3906s outperform them considerably.
Having no emitter resistors (in several places) is also a problem. It should still work, but expect lopsided waveforms, particularly at high current (= thermal imbalance) and low current (= Vbe mismatch).
Tell Hans. I assume he knew this was a problem but was being compensated for by matched transistors? Maybe I should simulate PNP transistors with hFE = 10?
Yes, both of those methods are completely absent, because they aren't required in monolithic circuitry. There are many gotchas in translating a monolithic circuit into discrete components!
You mean two transistors with the same nets for all three terminals, right? I could just stack another 2N3904 on top of that one? I can physically pull that off I think and test it with the board I have now. I will add that to the simulation and see what happens.
Yup!
Tim
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I'm going to assume that there's a solid ground plane on the back side of the board.
There is
You'll need to decouple every point that connects to Vcc.
You have to be kidding me, how then does any IC work? ICs don't contain a bunch of internal caps for every transistor and use typically only one for the whole circuit.
Then I suspect you'll need a collection of other caps to stop bits oscillating.
See my last comment.
Have you included the strays in your board layout into your model?
That gets done in IC design, but line lengths are much much much smaller.
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Matched transistors.
I suspect that's the least of the issues, too much gain, both at DC and at RF will both cause grief.
It might be fun to assign different transistors to the spice model to see the effects of unmatched transistors, or possibly just changing some parameters on a random basis across the model, though it is probably better to break it down into different segments to see the effects of mismatch and temperature on a block by block basis.
:phew: Actionable advice using only 79 words in 8 lines! :-+
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Yup!
Tim
Doing that gets results. It changes the waveform into something closer to a triangle, though it is not very clean anymore, and really increases the frequency. I will have to add that transistor and see if it does anything IRL.
(https://www.eevblog.com/forum/beginners/figuring-out-why-an-actual-circuit-is-not-working-like-the-simulated-circuit/?action=dlattach;attach=181246)
(https://www.eevblog.com/forum/beginners/figuring-out-why-an-actual-circuit-is-not-working-like-the-simulated-circuit/?action=dlattach;attach=181248)
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Your intuition was right. Doubling up Q11 makes the circuit work, though it isn't a quality triangle wave and the voltage swing is very small compared to the original specs or the original simulation.
(https://www.eevblog.com/forum/beginners/figuring-out-why-an-actual-circuit-is-not-working-like-the-simulated-circuit/?action=dlattach;attach=181253)
Second board same results @ ~122KHz
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Hmm, it should still be on the same thresholds. Something else is going batty.
Tim
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Can you post the LTspice .asc file?
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Can you post the LTspice .asc file?
Sure, I would love some expert advice. This was my first simulation ever. So if I did something really stupid, it should not come as a surprise.
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Here is my test board too if it matters. You can see Q11 is doubled up now and there is a little bit of a miss around it.
(https://www.eevblog.com/forum/beginners/figuring-out-why-an-actual-circuit-is-not-working-like-the-simulated-circuit/?action=dlattach;attach=181396;image)
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Hi
I as able to get the IC version of the circuit from the book working.
I reduced the size of each transistor to about 1/10 the size as it
would be on a chip. You can see in the attached image a 1Mhz triangle wave.
It is very close to the waveform the book shows.
For you circuit...I would start by using lower gain transistors.
good luck.
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Hi
I as able to get the IC version of the circuit from the book working.
I reduced the size of each transistor to about 1/10 the size as it
would be on a chip. You can see in the attached image a 1Mhz triangle wave.
It is very close to the waveform the book shows.
For you circuit...I would start by using lower gain transistors.
good luck.
Hey, thanks for all that. I am certainly learning something here. I have a bunch of questions though.
1. You reverted the resistor values back to Hans' values. I was using standard values so I can actually get a chip resistor with that value. I will resimulate with your values, but do you think it matters much?
2. Adding those output nets TRIANGLE, SQUARE, and R was just for convenience, right? That doesn't seem to affect anything. What is the need for the R "output"?
3. Why did you move the voltage source from the right to the left? Any reason?
Most importantly:
4. How do you specify a transistor model to use for your transistor? When I right-click on any transistors all I can do is "Pick New Transistor" and then use the list of commercial choices. I see no way to pick "NP" or "PN" and I don't understand how you specified "NP .1" or "PN .1" or why those names instead of just "NP" or "PN". Knowing this would be extremely helpful, I can't figure it out.
5. What transistors could I possibly use that have a close match to the simulation values you used for NP and PN? What might be a good choice?
Thank you for all your help so far.
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You'll need to decouple every point that connects to Vcc.
You have to be kidding me, how then does any IC work? ICs don't contain a bunch of internal caps for every transistor and use typically only one for the whole circuit.
Decoupling generally needs to be electrically close to the thing its decoupling. Everything in a low speed IC is pretty close to the Vcc pin, and a single decoupling capacitor (or a pair of high and low value ones) near the Vcc and Vss pins can work well. In a high IC decoupling between different areas of the chip becomes a problem, and a lot more care is needed with decoupling. In some fast ICs half the pins are Vcc and Vss. That's not just to carry high currents. Its also about decoupling. For a discrete circuit spread across a substantial area of PCB localised decoupling is usually necessary.
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Hey, thanks for all that. I am certainly learning something here. I have a bunch of questions though.
1. You reverted the resistor values back to Hans' values. I was using standard values so I can actually get a chip resistor with that value. I will resimulate with your values, but do you think it matters much?
I changed the values back to the original just to check that the circuit actually worked as drawn in the book.
One error was RBM6 (R14 on your schematic) it is shown as 17 ohms, should be 17k.
2. Adding those output nets TRIANGLE, SQUARE, and R was just for convenience, right? That doesn't seem to affect anything. What is the need for the R "output"?
Yes...for convenience. No...Don't know what "R" is for.
3. Why did you move the voltage source from the right to the left? Any reason?
Just did....ignore it.
Most importantly:
4. How do you specify a transistor model to use for your transistor? When I right-click on any transistors all I can do is "Pick New Transistor" and then use the list of commercial choices. I see no way to pick "NP" or "PN" and I don't understand how you specified "NP .1" or "PN .1" or why those names instead of just "NP" or "PN". Knowing this would be extremely helpful, I can't figure it out.
I actually used a text editor to edit the .asc file. But if you rht-clk on the transistor model text, a dialog will pop up and allow you to change it, then just type: "NP .1", w/o quotes. Doing so specifies "NP" as the model and ".1" is the size (area) of the device. default = 1. The size is a multiplier and increases or reduces all params for the device. For example 'NP 2" is the same as placing two transistors in parallel. The book your using is meant for IC designs, so keep that it mind when analyzing the circuits. IC's don't use transistors like you buy of the shelf and many of the adjustments are made by varying the size of the BJT.
5. What transistors could I possibly use that have a close match to the simulation values you used for NP and PN? What might be a good choice?
Thank you for all your help so far.
I'll leave that for you to research..
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I changed the values back to the original just to check that the circuit actually worked as drawn in the book.
One error was RBM6 (R14 on your schematic) it is shown as 17 ohms, should be 17k.
In the original post (see top of this post) I linked in Hans' schematic from his online book and that schematic has that resistor listed as 13K. I changed it to 12K to make it a standard value. I didn't use the value in the printed book or show the printed book's schematic. It's R14 in my schematic because it is R14 in Hans' schematic from the online corrected edition.
I actually used a text editor to edit the .asc file. But if you rht-clk on the transistor model text, a dialog will pop up and allow you to change it, then just type: "NP .1", w/o quotes. Doing so specifies "NP" as the model and ".1" is the size (area) of the device. default = 1. The size is a multiplier and increases or reduces all params for the device. For example 'NP 2" is the same as placing two transistors in parallel. The book your using is meant for IC designs, so keep that it mind when analyzing the circuits. IC's don't use transistors like you buy of the shelf and many of the adjustments are made by varying the size of the BJT.
That is what I figured but that box is read only on my machine. Maybe I will be editing the ASC file myself. I wonder why it is locked down. Maybe there is a parameter that needs to be set somewhere.
I'll leave that for you to research..
OK, thanks. I am just concerned there will be none to find. I would think that modern transistor designs are done to maximize gain.
Thanks for everything. I will see what I can do with this.