As it happens, I just finished a project that uses three closely related regulator models (the LT3045-1 positive 500mA and the LT3093 200mA negative) and I sweated over the PCB design. (Ultimately, I closely followed the demo board layouts.)
It looks like you've followed the NPN follower design from p.27 of the datasheet, and I'll be honest that I'm not entirely sure how some of the subsequent points are best handled in that configuration.
The only things that really stand out to me are the connections to R4 (Rset), C5 (Cset, i.e. Rset's stabilization cap), and their connection to the output caps C14 (NPN follower output cap) and C16 (LT3042 OUT cap).
I see that you followed the datasheet's instruction to Kelvin connect to the load ground, but I'm not so sure that's what they had in mind. If you look elsewhere in the datasheet, and on the (single-chip) demo board layout, they've a) placed the output cap REALLY close to the IC (a second, optional cap is shown in the demo board right by the output jacks at the edge of the board), and b) it uses a Kelvin connection to both ends of the output cap. Since you want the feedback loop to be physically as small as possible (so you don't have error currents flowing over longer distances), I'd think you'd want to have both C14 and C16 really close to the IC, and with their grounds as close as possible to each other, on the output side. Your layout creates a very long route for the Rset resistor's ground, but above all, has separated its stabilization cap from that same route. So rather than stabilizing, I think you've created two different routes for the high-frequency noise and the set current.
I'd see what happens if you desolder R4 and then solder it on top of C16, directly in parallel.
Go back and re-read the datasheet and the user guides and PCB layouts to the two demo boards. You'll notice that the multi-chip demo board doesn't use all of the techniques described in the datasheet (whereas the single-chip demo board uses most of them). Studying them closely will give you an idea of how they lay them out for top performance. The datasheet warns about ESR and ESL outside the feedback loop reducing performance.
One design approach your board definitely doesn't follow is to keep the input traces exactly the same (on different layers) to reduce magnetic coupling of noise. Study the single-chip demo board in particular to see how they did that.
Finally, I have no idea how much noise the NPN follower adds. I assume it's not zero, but I couldn't begin to guess how big an effect it has.