Final Low-Side Linear Adjustable Load?

[LooseJunkHater]

Background: I've been slowly asking questions about this topic + learning about it (slowly) for years. 1. 2. 3. 4., and I think I'm almost done. Obviously the circuit has gotten more complex over time as my knowledge grew, but I'm genuinely happy with it.

My most current iteration is here.



What the circuit does: It uses two op-amps; one for controlling the FET (so that the FET is acting essentially as a variable resistor), and another op-amp in a comparator-configuration. The purpose of the comparator is so that the FET is held non-conductive until an actual input voltage is detected (preventing a sudden current-spike when a load is connected, before the op-amp has time to regulate the FET).

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The reason/question for this post: I'm wondering if anyone can provide specific suggestions on two key areas;



1. Is this resistor really needed? My rationale for it was to slow the charge/discharge of the small 100pF capacitor, but maybe at such a low capacitance, it doesn't matter?

2. Should this configuration of capacitor + resistors be changed up? My rationale for the configuration is to slow the charge/discharge of the small 1n capacitor (which I imagine is probably too-large), slow the charge/discharge of the FET gate, as well as prevent oscillations from occurring.

Thanks!

[Vovk_Z]

I use voltage detector in my loads too (using LM2903 I guess). My threshold is about 1.0-1.5VDC, which is good for my purposes (I work with voltages 5-250 VDC, not smaller then this).
 I use it with a small positive feedback to form a Schmidt Trigger with clear turn-on and turn-off. (Addiional 10-20M resistor in positive feedback line).
I guess it is good to slow down it a bit. But I woud rather put input filter before this comparator to its input divider, where it will help more. I use like 4-5M to 200k divider for my input voltage range (it divides input viltage by 20-25 in my case). Voltage level to compare is 35-50 mV at another comparator input (30 mV is a minimum). If you are not sure in you skills use 100 mV voltage level. 
I find LM4041D12 pretty suitable and cheap to use as a 1.2VDC rated Zener.

[MariuszD]

1. Is this resistor really needed? My rationale for it was to slow the charge/discharge of the small 100pF capacitor, but maybe at such a low capacitance, it doesn't matter?

I suppose that resistor 1kOhm and capacitor C=100pF does nothing. Time constant Tau=R*C=1kOhm*100pF=100ns but this amplifier has slew rate 0,6V/us.

[ledtester]

Another way to do it... (see attachment)

the LM393 pulls down the + input of the controlling op-amp when no input voltage is detected.

Another reason I can think of for altering the set-current input of the op-amp instead of the sense current input is if you wanted to monitor and record the load current like with an ADC.

[LooseJunkHater]

I use voltage detector in my loads too (using LM2903 I guess). My threshold is about 1.0-1.5VDC, which is good for my purposes (I work with voltages 5-250 VDC, not smaller then this).
 I use it with a small positive feedback to form a Schmidt Trigger with clear turn-on and turn-off. (Addiional 10-20M resistor in positive feedback line).
I guess it is good to slow down it a bit. But I woud rather put input filter before this comparator to its input divider, where it will help more. I use like 4-5M to 200k divider for my input voltage range (it divides input viltage by 20-25 in my case). Voltage level to compare is 35-50 mV at another comparator input (30 mV is a minimum). If you are not sure in you skills use 100 mV voltage level. 
I find LM4041D12 pretty suitable and cheap to use as a 1.2VDC rated Zener.

Do you have an image representing this? I can't really visualize it in my head.

[LooseJunkHater]

Another way to do it... (see attachment)

the LM393 pulls down the + input of the controlling op-amp when no input voltage is detected.

Another reason I can think of for altering the set-current input of the op-amp instead of the sense current input is if you wanted to monitor and record the load current like with an ADC.

It does look like your IC1A (LM393) is indeed doing a similar job to my LM324, sensing the input voltage, and instead effecting the in+ of the op-amp (while I control in-). I'll mess around with your circuit in Falstad. I'll definitely be using your idea of D3 to protect the in+ of the voltage-sensing op-amp, as it reduces my BOM count by one, but serves the same function.

I can also see that you're using OP1B (LM258N) because you're using a much smaller current-sense resistor (0.01ohm vs my 0.1ohm), which will help for measuring the smaller voltage drop.

In regards to your circuit, I'm not quite sure what D2 (5.1v zener) is being used for?

[LooseJunkHater]

2. Should this configuration of capacitor + resistors be changed up? My rationale for the configuration is to slow the charge/discharge of the small 1n capacitor (which I imagine is probably too-large), slow the charge/discharge of the FET gate, as well as prevent oscillations from occurring.

Also still waiting for feedback on this part of my circuit. Any feedback welcome

[ledtester]

In regards to your circuit, I'm not quite sure what D2 (5.1v zener) is being used for?

I think it's just to protect the MOSFET.

Btw - here's a forum thread about the -2G version of the board:

https://www.eevblog.com/forum/beginners/understanding-this-dc-load-circuit/

Reply #6 seems to have some good analysis. It also talks about preventing bad behavior in case the supply voltage is too low.

[Vovk_Z]

Here is my circuit, in the atachment.
It is mostly accurate about values, but not 100%.
Capacitors C1, C2 (showed as 1 nF) usually must be 3-10 nF to it was really stable.

[LooseJunkHater]

Here's my most-recent iteration of the Falstad circuit. I did actually build most of this circuit IRL, but I accidentally killed the FET's by going over the SOA.



Noteworthy changes:
- Reverse polarity protection via a diode
- Improved input offset voltage correction circuit inspired by this Analog.com document
- Zener diode for FET protection (as suggested by other comments in this post)
- 100k resistor to ensure the FET gate is held low



Future ideas:
- Adding some (manual or automatic) ranging to the circuit, so that when 0.1v-30v input --> max current 10a, 31v-50v --> max current 3a, 51v-100v --> max current 1a. The purpose of the ranges is to not exceed the SOA of the FET's, but this ranging design would greatly increase the complexity. Instead, I just plan to build multiple modules which handle different ranges, abiding to the SOA of the FET's.
- Adding a window comparator to prevent the circuit from running when too-high of an input voltage is injected (therefore saving the FET's).