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Finite State Machines

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logictom:
I'm just doing some revision and have a question on FSM's.
I'm given the following diagram

The questions are:
1. Determine if the FSM is Mealy or Moore
2. Detect redundant states in the FSM
3. Eliminate redundant states and redraw.

My answers:
1. Mealy

2.

S3 and S4 are redundant

3.

Redrawn

Can anyone confirm if this is correct or not?
Last time I did this was about year and a half ago and I only have one example in my notes.
Thanks ;)

armandas:
1. Output depends on the state as well as input, so Mealy.
2. S3 and S4 are the same, but I'd say that only S4 is redundant and have to be removed. Why create a new state?
3. Looks right, but, as mentioned above, A may be left as S3.

logictom:
I wasn't too sure about if needed to define as a new state or could just merge them.
Thanks for clearing that up :)

logictom:
I've another question but this one you have to derive the FSM from some Verilog, I have very little experience with Verilog but think this is correct.

--- Code: ---module fsm1 (y, clk, reset, e, r);

input clk, reset, e, r;
output y;
reg y;

parameter [3:0] A = 4'b0010,
B = 4'b0001,
C = 4'b1000,
D = 4'b0100;

reg [3:0] state, next;

always @ (posedge clk or posedge reset)
if(reset) state <= A;
else state <= next;

always @ (state or r or e) begin
if(!e) next=state; else
case (state)
A: if (r) next = D; else next = B;
B: if (r) next = A; else next = C;
C: if (r) next = B; else next = D;
D: if (r) next = C; else next = A;
default: next = A;
endcase
end

assign y <= state[0] | state[2];

endmodule

--- End code ---

The FSM:


This FSM being a Moore machine Mealy machine because it has more than one output?
Is this correct?
Thanks again :)

Mechatrommer:
may i know whats that XX/XXXX symbols stand for?

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