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Flipflop is unstable

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ratatax:
Hi,

I made a clock divider using two flip-flops, which takes a GPIO from my raspberry Pi as input :



It should divide the input clock by four.

Problem : it mostly works but output is not reliable and very sensitive to any noise... Like it gets better if I put my fingers on some pins... and gets much worse if I try to probe it with my scope.

Signal input is about 200Khz and output should be 50Khz (divided by four), I use NC7SZ74's from On Semiconductor : https://datasheet.lcsc.com/szlcsc/ON-Semicon-ON-NC7SZ74K8X_C128370.pdf

Is there something obviously wrong I my schematic ? Should I put resistors between some lines ?

fourfathom:
Your schematic looks fine, except that you don't show any bypass capacitors on the VCC pins.  This is probably why you are seeing the noise problems.  Connect 0.1uF ceramic capacitors between VCC and GND as close to the ICs as possible.  Make sure that your ground connections are short.

There are easier ways to do a divide-by-four, but what you have should certainly work once you get your layout noise problems solved.

tggzzz:
You are using fast parts, and they will have very high frequency components in the output signals defined by the transition time not the clock period.

If you are using solderless breadboards, you will fail due to the inductance of all the interconnection wires.

If you are not using solderless breadboards, you may still fail unless you have decoupling capacitors plus direct connections (not wires, and preferably a continuous ground plane).

Realise a wire is L=1nH/mm, then do the calculation of V=Ldi/dt and realise that V is added/subtracted to signal voltages. dt is the transition time (probably 1ns or less) and di=3.3C/dt, where C is the a load capacitance (assume 10pF) and 3.3 is the voltage swing.

ratatax:

--- Quote from: tggzzz on August 03, 2019, 02:17:00 pm ---You are using fast parts, and they will have very high frequency components in the output signals defined by the transition time not the clock period.

If you are using solderless breadboards, you will fail due to the inductance of all the interconnection wires.

If you are not using solderless breadboards, you may still fail unless you have decoupling capacitors plus direct connections (not wires, and preferably a continuous ground plane).

Realise a wire is L=1nH/mm, then do the calculation of V=Ldi/dt and realise that V is added/subtracted to signal voltages. dt is the transition time (probably 1ns or less) and di=3.3C/dt, where C is the a load capacitance (assume 10pF) and 3.3 is the voltage swing.

--- End quote ---

Thanks, yes all of this is on a prototype board with a real mess of wires all over the place, I noticed disconnecting another chip on 3.3V made things better so yeah probably a noise problem that will be solved once put on a real pcb ! Bypass capacitors had no effect but I can't put them close to the IC pins, 0.5mm pitch by hand is a nightmare  ;D




--- Quote from: fourfathom on August 03, 2019, 01:45:23 pm ---Your schematic looks fine, except that you don't show any bypass capacitors on the VCC pins.  This is probably why you are seeing the noise problems.  Connect 0.1uF ceramic capacitors between VCC and GND as close to the ICs as possible.  Make sure that your ground connections are short.

There are easier ways to do a divide-by-four, but what you have should certainly work once you get your layout noise problems solved.

--- End quote ---

@fourfathom i'm interested by the easier way to do the frequency division, could you do this with only 1 component ?

Kleinstein:
There are slow chips that are less sensitive. They also get away with a slower rise time for the clock. The classic 74HC74 has 2 such flipflops in one case. 74AC74 would be a little faster than classic HC. 74HC74 usually still works on the breadboard.
The are also ready made ripple counters that could be used, though usually not small than 74HC74, just more stages.

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