Floating inputs cause AND circuit to produce High? Why? 60 second video.

[renzoms]

https://youtu.be/XRKPNVEovEM

I tied two NAND gates to make an AND gate. The inputs of the first NAND are tied together too.

When left alone, the LED seems to react to movement SOMETIMES. Sometimes it just stays off too. Video shows the phenomenon 

[rstofer]

The output of a logic gate is not defined for floating inputs.  You need to be below the logic 0 threshold or above the logic 1 threshold.  Get the values from the datasheet.

[Picuino]

[IanB]

https://youtu.be/XRKPNVEovEM

I tied two NAND gates to make an AND gate. The inputs of the first NAND are tied together too.

When left alone, the LED seems to react to movement SOMETIMES. Sometimes it just stays off too. Video shows the phenomenon 

You should be careful. When I was young (many years ago) and learning about digital logic, the industry was making the transition from TTL logic to CMOS logic. TTL was very robust and safe, but CMOS was sensitive to static. It was a golden rule never to leave inputs floating because of the danger of damaging the chip.

Maybe today the chips have clamp diodes for input protection, but there still may be a danger. It is a pretty good rule of thumb to avoid floating potentials in any circuit. Always make sure your voltages are well defined. If you know where your voltage is, you can avoid it going where it shouldn't be.

[emece67]

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[renzoms]

Picuino, Thanks. I think that solves it.

rstofer, Thanks. Good to know. I checked the data sheet and think it's 2V (threshold High). I think my body was produced the signal. (I am not grounded 😈).

IanB, Thanks. I will keep those clamping diodes for input protection in mind, I'm working towards experimenting/building something with those.

emece67, 7400. The circuit: Both inputs of a NAND tied to an input (floating/5V/ground). Then the output of that NAND becomes the input to both inputs of another NAND. Effectively an AND gate (with it's inputs tied together). 664 ohm resistor. 3V LED. 5V source.

[rstofer]

The answers are in the datasheet!

For a standard 7400, the logic 1 threshold is 2.4V, we need to be above that.  So, we tie a 10k resistor between the input and +5.  There's actually a reason for pulling high rather than low.  The input high current is 40 uA and the input low current is -1.6 mA.  It's negative because the current is flowing out of the pin.  That's 40 times more current!

But look at the logic 1 output current!  It's just -0.4 mA, sourcing so it couldn't pull the pin high against the resistor to ground.  OTOH, the gate can sink (pull down) 16 mA so the pullup current is no problem.  That's the reason that we ALWAYS used pull-up resistors and almost never pull-down resistors.

It all comes down to numbers and datasheets:

https://web.mit.edu/6.131/www/document/7400.pdf

This is less of an issue with CMOS but it still better to define a logic level.  Floating CMOS inputs tend to create oscillation and heating.

[emece67]

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[renzoms]

rstofer, Thanks for that - helping me out. Learned a lot and understood clearly.

emece67, Interesting I will keep that in mind as I cross that (TTL) in the text. Thanks.

[gcewing]

Modern CMOS inputs are usually fairly well protected against ESD, but it's still a really bad idea to leave them floating. They have very high impedance and will happily respond to any stray electric fields in the vicinity. Not only does this lead to unpredictable behaviour, if the input hangs around between the high and low thresholds for very long, the top and bottom transistors both turn on, which can pass excessive current and overheat the chip.

TTL inputs will float high very predictably, but it's still recommended to use a pullup resistor of 1k-10k or so for noise immunity.