Author Topic: Flyback simulation voltage spikes?  (Read 2883 times)

0 Members and 1 Guest are viewing this topic.

Offline ifonlyeverythingTopic starter

  • Regular Contributor
  • *
  • Posts: 144
  • Country: us
Flyback simulation voltage spikes?
« on: May 14, 2023, 07:42:31 pm »
I want to build my very first flyback converter with 12V DC input and +/- 15V DC output, 100mA maximum for each output. I want continuous conduction mode (CCM) due to lower output ripple, as this circuit will be used to power analog circuitry. I have some UC3845 ICs, EE10 transformers (PC40 material), and 4N27 optocouplers on hand that I'd like to use.

I arbitrarily chose 150 KHz switching frequency and plugged my requirements into equation (9) from this link to get ~260 uH primary inductance. I used equation (1) to get a turns ratio of 1.31.  https://www.edn.com/power-tips-77-designing-a-ccm-flyback-converter/ My transformer has an AL = 0.9 uH/N^2, so 17 primary turns yields ~260 uH. Secondary turns are 17 * 1.31 turns ratio ~ 23 turns for ~480 uH inductance.

I believe my requirements are well within the saturation limits of an EE10 transformer. I used the Bmax formula on this page https://www.homemade-circuits.com/how-to-design-and-calculate-ferrite-core-transformers-for-inverters/ with an Ae cross sectional area for my EE10 transformer of 12.10 mm^2. The results fell within the ~0.3 T (~3000 Gauss) saturation magnetic flux density for PC40 material. I haven't tried physically constructing this yet but I'm hoping all of these turns will fit on it...

Diodes are just a placeholder, I have some 1N5822 that might work IRL. Snubber circuit is also a placeholder as I don't really understand the calculations yet.

I threw this together and LTspice with some compensation values I found in other online schematics and it appears to work. I can see it performing CCM for the 150 ohm dummy load on each output, which is great. The problem is that I'm seeing large spikes on the output, inductors, MOSFET gate, etc. What is causing this and how can I fix it? Playing with the snubber values doesn't seem to fix anything.





 

Offline ifonlyeverythingTopic starter

  • Regular Contributor
  • *
  • Posts: 144
  • Country: us
Re: Flyback simulation voltage spikes?
« Reply #1 on: May 14, 2023, 08:07:04 pm »
ASC file attached. It's not letting me attach the TL431 .sub or .asy files, but:

Code: [Select]
* TL431 Current Regulator
.subckt TL431 CATHODE ANODE REF
Q1 N004 N003 N001 0 P
Q2 ANODE N002 N001 0 P
Q3 CATHODE N005 ANODE 0 N
R1 N002 ANODE 600k
R2 REF N002 648k
I1 CATHODE N001 5µ
V1 N003 ANODE 1.2V
Q4 CATHODE N004 N005 0 N
R6 N004 ANODE 640k
.model N NPN(BF=250 Cje=.5p Cjc=.5p Rb=500)
.model P PNP(BF=120 Cje=.3p Cjc=1.5p Rb=250)
.ends TL431

Code: [Select]
Version 4
SymbolType BLOCK
LINE Normal -17 16 0 -15
LINE Normal 16 16 -17 16
LINE Normal 0 -15 16 16
LINE Normal -15 -15 -24 -24
LINE Normal 0 -15 -15 -15
LINE Normal 16 -15 0 -15
LINE Normal 24 -7 16 -15
LINE Normal 0 -48 0 -15
LINE Normal 0 16 0 48
LINE Normal -7 -1 -48 -1
RECTANGLE Normal 48 48 -48 -48
WINDOW 3 12 62 Left 0
WINDOW 0 13 -61 Left 0
SYMATTR Value TL431
SYMATTR SpiceModel TL431.sub
SYMATTR Prefix X
SYMATTR Value2 TL431
SYMATTR Description Programmable Shunt Regulator TL431
PIN 0 -48 NONE 8
PINATTR PinName CATHODE
PINATTR SpiceOrder 1
PIN 0 48 NONE 8
PINATTR PinName ANODE
PINATTR SpiceOrder 2
PIN -48 0 NONE 8
PINATTR PinName REF
PINATTR SpiceOrder 3
 

Offline Benta

  • Super Contributor
  • ***
  • Posts: 6921
  • Country: de
Re: Flyback simulation voltage spikes?
« Reply #2 on: May 14, 2023, 08:27:01 pm »
Unreadable, even with a magnifying glass. Sorry.
Try limiting/cutting the screen area before posting. Using .png is best.
 

Offline ifonlyeverythingTopic starter

  • Regular Contributor
  • *
  • Posts: 144
  • Country: us
Re: Flyback simulation voltage spikes?
« Reply #3 on: May 15, 2023, 01:04:12 pm »
Unreadable, even with a magnifying glass. Sorry.
Try limiting/cutting the screen area before posting. Using .png is best.

I think it's the forum software causing scaling issues, the screenshot is .png at native resolution. If you right click and open it in a new browser tab/window it becomes easier to see?

I think I found a solution to my problem. Apparently LTspice shows these spikes with perfect transformer coupling. I modified it to K=0.97 (no idea if this is realistic for a hand-wound transformer) and the spikes are gone. Also played around with some of the other values, somewhat haphazardly, and swapped out with LT1243 (50% duty cycle limit) because I was getting weird double pulses with the LT1245 (~100% duty cycle limit.) Am I correct in believing that since my PWM duty cycle is limited at 50%, I do not need any slope compensation?



 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 22435
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: Flyback simulation voltage spikes?
« Reply #4 on: May 15, 2023, 07:36:41 pm »
Am I correct in believing that since my PWM duty cycle is limited at 50%, I do not need any slope compensation?

Ah yes... this most awful of oft-repeated falsehoods. :palm:

But, let this be a lesson on the quality of appnotes.  Even some academic articles and books repeat it, sadly!

The error is this: note what condition 50% relates to.  In almost all setups, the turns and voltage ratios are such that CCM occurs at 50% duty.  This is the least stressful case for FET, diode and inductor, so it's the most common setup.

CCM is actually what's important.  Every single time they say "50% duty", they mean "CCM".

If you're using a different turns/voltage ratio, this point will fall somewhere else.  You can indeed get period doubling at, like, 10% say -- doesn't matter, it can be arbitrarily low, if the voltage ratio is weird enough.  Consider startup conditions, where the output voltage is very low and the inductor doesn't discharge quickly: duty can be quite low in this condition and still be deep into CCM.

You need slope comp to avoid chaos -- literally.  In fact, fascinatingly enough, the peak current mode control, for given peak current reference, is an implementation of the logistic map function, a chaotic system.

Generating the bifurcation diagram is not exactly trivial unfortunately, so it's not a beauty you're going to see pop up on your oscilloscope; but in short, if the inductor retains some current from the previous cycle (it's nominally in CCM), that initial offset adds to the next pulse, making it shorter than expected.  The difference builds up until one pulse crosses into DCM (setting the inductor's state), and the cycle repeats.

For higher current setpoints, it bifurcates again, into 4, then 8, etc. discrete pulse widths before resetting.  Pretty quickly thereafter, it explodes into myriad states, which might not be easily counted, or indeed cannot be counted due to errors in the circuit (resulting in randomness instead).

The bifurcation diagram is plotting the %duty (x, rescaled) for each pulse in the cycle, versus current setpoint (r, also rescaled).  You can see there are regions of stability here and there, in the right side regions, including a three-state loop (and then 6, etc.).  Pretty crazy.

I won't go into further detail about the effects -- there are excellent papers (maybe even videos, I'm not sure?) out there, now that you have some keywords to search on -- just suffice it to say, for control purposes, we want smooth and consistent control without unexpected behavior, and therefore need to operate low on the curve (r < 3).  Which means we must stay in DCM.

What slope compensation does, is skew the system, so that it can remain stable up to higher current setpoints, that is, less than 100% ripple fraction (RF being ΔIpk / Idc, as seen by the inductor).  Roughly speaking, the maximum stable ripple fraction equals the fraction of Isense coming from the switch.

If it's pure current mode (switch current only, no slope), it's not stable in CCM, but switch current is perfectly controlled (peak never above setpoint, at least for very long).

If it were pure voltage mode (slope only, no switch current sensed), it would be stable at any current -- but we wouldn't know what current is flowing through the switch and it's easily blown up.  No good.

This is a continuous case between extremes, so we must choose a compromise between losing accuracy of switch current (which raises switch losses at extreme conditions i.e. high Vin, high Iout, low Vout), and lowering ripple fraction (which reduces inductor losses).  Typically 50 to 30% ripple fraction is as low as you want to go with peak current mode control -- which worsens peak switch current control by 2-3x, which is usually tolerable.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 22435
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: Flyback simulation voltage spikes?
« Reply #5 on: May 15, 2023, 07:52:32 pm »
As for the peak overshoot and ringing -- simply put an R+C across each winding.  Probably one is needed on the primary side, which addresses primary-referred leakage, when the primary is open and the secondary is shorted (meaning an AC short, i.e. the secondary voltage is held constant during the discharge phase, by the diode and filter cap), and one on the secondary (when the primary is [AC] short and the secondary is open).

Choose capacitor such that it slightly dominates above node capacitance (so, Coss of the transistor, or Cjo of the diode, both measured at their respective nominal operating DC voltage), and resistor R = sqrt(LL / Coss) (or Cjo).  "Slightly dominates" meaning 2-4 times larger.

LL in turn is given by the coupling factor and winding inductance, LL = Lm * (1 - k^2).  Lm is Lp or Ls to get the primary- or secondary-referred leakage, respectively.

97% coupling is a bit low for flyback, but not unheard of.

If this is a custom wound part, understand that leakage is determined by the space between windings.  Minimize this space, to maximize coupling.  That means using multiple layers interleaved (alternating P-S-..), twisted pair, transmission line transformer techniques, etc.  Leakage is where a transformer is NOT simply two windings anywhere on a core -- the cartoon of two windings on opposite sides of a ring core is in fact the worst possible case here!

You may also want a dV/dt snubber on the primary side, i.e. a (D || R) + C network, where C is chosen such that it slightly increases rise time at maximum peak current, and R such that it dampens the free ringdown of the inductor (in DCM, i.e. both windings open-circuit, when Lp is the inductance from [AC] ground to the switch node).  If peak voltage is still too high, consider increasing C (but mind its impact on operation at light load), or use a peak voltage clamp snubber (which is what you have now).

Still higher amounts of leakage can be dealt with using either a [quasi-]resonant ("lossless") snubber, or two-switch flyback (or forward), or active clamp flyback.  But it's better to just fix the leakage in the first place, if you can.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Offline ifonlyeverythingTopic starter

  • Regular Contributor
  • *
  • Posts: 144
  • Country: us
Re: Flyback simulation voltage spikes?
« Reply #6 on: May 17, 2023, 11:18:50 am »
As always, thanks for the very detailed response. Will be sure to add some slope comp, and the R+C across windings did quiet down the ringing.

What is a realistic estimate for leakage % for a beginner's first hand-wound transformer?  ::)
 

Offline T3sl4co1l

  • Super Contributor
  • ***
  • Posts: 22435
  • Country: us
  • Expert, Analog Electronics, PCB Layout, EMC
    • Seven Transistor Labs
Re: Flyback simulation voltage spikes?
« Reply #7 on: May 17, 2023, 01:09:45 pm »
Beats me -- could be 1-10% for a crude, or even inappropriate, design, down to 0.1% or less for either a very tight one, or an entirely different kind of inappropriate (in that the leakage is normal, but the magnetizing inductance is too high).

Could you make a diagram of how you wound it, on what core, air gap if applicable, etc.?

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 


Share me

Digg  Facebook  SlashDot  Delicious  Technorati  Twitter  Google  Yahoo
Smf