EEVblog Electronics Community Forum
Electronics => Beginners => Topic started by: inanowire on May 05, 2023, 09:31:38 pm
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Hello Everyone,
I am fairly new to this so please bear with me.
I have been looking at reducing the static power consumption in an IC, and have been mainly focussed to reduce the parasitics in the wiring in the BEOL. However, I was wondering that whether in the FEOL, on an n-type transistor (thin film transistor) level - is there a figure of merit to explore? I have looked into ring oscillators and single inverters but not sure if a single transistor KPI could add value and provide a reasonable reference in this scenario.
Thanks,
AJ
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Do you have more unknown acronyms in stock? Pure Klingon, sorry.
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Sorry. Here you go -
IC - Integrated Circuit
FEOL - Front End Of Line (device level)
BEOL - Back End Of Line (interconnection)
FoM - Figure of Merit
KPI - Key Performance Indictors (such as Vth, Von, Ion, Isat, STS, Mobility)
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Power consumption optimizations in ICs has been extensively studied to the tune of trillions of R&D dollars at the process and design level. You are going to have to get dramatically more specific about what you are interested in.
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Thank you. I am mostly interested in understanding if there is a widely used figure of merit on a transistor level pertaining to power consumption. For example, for thin film transistors I was thinking along the lines of:
Measure current (Id) at voltage >>Vt
Calculate FoM = (Vt*Cg)/Id
Lower the FoM the better the device would be?
Id = drain current
Vt = threshold voltage
Cg = gate capacitance
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*WARNING* this is from the perspective of someone who spent the bulk of his career on full-custom, draw the pointy boats, draw the dull boats type chip design. The kind they did when Moses was floating down the river. But some of this applies to current times anyway.
If you are interested in *static* power consumption (that is, no signals are changing except for -- perhaps -- the clock) then BEOL is not where you need to look. Parasitic inter-track capacitance doesn't matter if there are no voltages changing. Even when the chip is active, parasitic interconnect capacitance doesn't account for any first-order effects. (Once you "do the right thing" in terms of wire dimensions and spacing, and sizing drivers to fit the load, interconnect is a signal integrity/timing/wearout issue, not a power issue.)
The major influence on static power consumption is leakage. This is often a trade between fast and leaky. But that's not a choice you get to make. The folks who designed the process have made it for you. Leakage, for a quiescent chip, is going to be determined by process and the width of your devices. (You can try to relate that to Idss, Vth, Vdd, and all that, but it will end in tears. The closest thing to the truth will be in the technology file from the foundry: a document that you are unlikely to see.). Certain structures may leak more than alternatives. (RAMs may leak more than register files. But the latter are bigger and not as efficient when it comes to dynamic power if it comes down to a choice. RF is the choice only when you can't shape your problem into a RAM.)
In particular, static power may be a function of Vt, Idss, Cg for some size transistor, but not in any useful way.
As a previous commenter said: billions of dollars, millions of hours, and thousands of graduate theses have been devoted to the various questions around static and dynamic power. One figure-of-merit isn't going to lead to any useful truth.
For a fixed Vdd, dynamic power will always boil down to something like superlinear in frequency. (Yes, the books may say CV^2 f but they leave out the dependence of C on f and assume the required dv/dt is linear in frequency. Neither is a good assumption.)
The figure of merit is going to depend on who asks the question. For chips that spend most of their time waiting for the next event two hours from now, static power is the primary consideration. For chips that never shut down and run full-tilt-boogie 24/7/365/end-of-the-universe, dynamic power vs. frequency and the frequency vs. Vdd curve will dominate the discussion.
This is a really really complicated problem.
Oh.. forgot to mention... when it comes to power efficiency, look to the architecture before you look at implementation and circuits.
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Thank you very much for such a comprehensive response, much appreciated.
I am the person who partly produces the process design kit (details with device performances). I am close to process and electrical performance of the discrete devices. I am keen on learning whether there are are device level metrics that could allow designers/modellers to benefit from. Individual KPIs such as Id, Von, Vth, mobility etc. are useful however I wonder if there is need for a figure of merit (some sort of RC constant?) that provides a more closer answer.
For example, we can control and physically change the device dimensions, carrier mobility, gate capacitance etc. to match it to the load to maintain speed while lower the power consumption.
I have explored it by moving to a ring oscillator to capture information like frequency, speed and power consumption however with my limited experience there I feel due to the buffer we are not really capturing the true information.
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Is this a startup or something? I'd be shocked if a big fab like TSMC didn't have methodologies in place already...
Tim
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Spot on! It is a startup.