Shift Register Problems

[gigavolt]

I have been trying to run a 74HC164 shift register using a 555 timer as a clock at ~1Hz, but have been running into an issue with what looks like double counting of the clock.  I can put data onto the shift register using a switch and it will sometimes work well, but often times the data will jump ahead by more than one bit in a single clock cycle.  Usually it will jump ahead by two bits instead of one, but I've also seen three and four.

I have tried adding decoupling caps to the IC (0.1uF) and have taken a look at the clock's rising edge (attached) which is faster than the recommended value for the part.  I've run out of ideas for debugging the circuit and thought I'd check if anybody here has suggestions.

[Psi]

Is it occurring with the 555 as well?  or just your switch input.
That's pretty common for a switch, the contacts bounce a lot and get double clocked.

A decoupling cap for VCC isn't enough, you also need to filter the clock input to remove the bounce from the switch.

Put a cap between shift reg input and gnd, then add a resistor to link that to the switch.

Try 20k and 1uF  for a 8hz low pass filter, that should filter your mechanical switch enough to smooth it out.

You will want to change those values when clocking from the 555 timer.

[gigavolt]

No, the 555 seems as stable as can be.  I'm using the switch for the data input, not the clock.  If I close and hold the switch and just let the shift register run, then I still see the double clocking issue, so I don't think it's a problem with bounce.  I did try adding a tiny low pass filter to clean up the edge of the clock (bringing up the rise time to 400nS), but it didn't help.

[garethw]

It may be worth checking all unused inputs are held either high or low (depending on the input). A floating input can cause all sorts of wonderful results.

Gareth

[ivaylo]

Or if the front produced by the 555 is too slow the 74 series may be unstable between what’s defined as 0 or 1. Seen it happen...

[garethw]

Or if the front produced by the 555 is too slow the 74 series may be unstable between what’s defined as 0 or 1. Seen it happen...

This was my first thought. The datasheet gives a specification of 500ns max transition time for the SN74HC164 (Using a TI datasheet). The clock rise time is measured at 314ns as per the attached image.
It may be worth checking the specific manufacturers datasheet as this may differ and your IC might have a shorter Max value.

[garethw]

I have just checked a different manufacturers datasheet for the 74HC164, this time from Nexperia. They give a Max transition time of 139ns. Your 555 clock edges would be too slow for this particular IC.
Check what brand 74HC164 is and find the specific datasheet. 

Gareth

[StillTrying]

A 555's output should switch faster than that ~100ns at 5V.

On a breadboard the 0.1uF decoupling across a 555 has to be as close as possible to the pins 1 and 8, to prevent the 555's switching spikes getting on to the breadboard's Vcc or GND. A similar effect can happen from the timing cap if there's very low resistance between the cap and discharge pin.

[gigavolt]

Thanks all, I tried adding better decoupling for the 555 and shift register and made a shorter jump to get to the clock input.  I got the rise time down to ~150nS, but still see the issue.  I'm using the ON Semi part which has the max rise time as 500nS.



I'm questioning whether the issue is with double counting the clock now.  I've attached some plots of me messing around with the input.  Ch1 is clock and Ch2 - Ch4 are outputs 1-3.



Most times, instead of just putting the input onto the first bit, both the first and the second go high with the third behaving normally.  Bringing the input low shut all of them off on the next clock cycle.  Sometimes it seems to behave normally like in attachment 4 where the high input propagates like it should.  Unfortunately, I don't have a logic analyzer, so I can't show more bits than that.

@garethw, I checked and don't have any floating inputs.  The only pins I left unconnected are outputs 4-8 (and I suppose 1-3 which are just going to the oscilloscope).

[StillTrying]

"Most times, instead of just putting the input onto the first bit, both the first and the second go high with the third behaving normally."

Yes it looks like not all stages double clock.
Is the 74HC164's decoupling very close to the power pins. Those breadboard links are often bad, I've sometimes used 2 for GNDs and power.
The traces look quite noisy to me for 1v/div and 5V/div.

You could try a ~2k2 pull resistor on the 555's output to speed up the last 1.5V from V+.

[gigavolt]

I think I have another clue to this problem  I was able to catch one of the "double clocking" events in action using my oscilloscope.  Ch1 is clock and Ch2-3 are outputs 1 and 2.  I'm probing the clock line right on top of the shift register using one of those rigid ground leads right on the end of the probe.  It looks like the clock line is ringing a ton and it felt like the double clocking events were more rare when I had the oscilloscope probe connected.  Do you guys think that this could be the problem?  Any recommendations on fixing it?

@StillTrying, the 74HC164 is decoupled the same as the 555 with a 0.1uF right on top of it.  I also added a 1uF ceramic just in case, but saw now change.

[gigavolt]

Fixed it!  I added ~100pF to the clock inputs of the shift registers and I don't see double clocking anymore.  I'm guessing that this is due to the inductance of the wires I'm using to connect the two chips along with the capacitance of the breadboard conspiring to create some weird filter.  I'm planning to put the design on a PCB in the future.  Do you guys think I need to add the capacitors there as well?

[StillTrying]

"I'm guessing that this is due to the inductance of the wires I'm using to connect the two chips along with the capacitance of the breadboard conspiring to create some weird filter."

Yes, it looks like the fast 10ns falling edges of the outputs are getting back into the rising clock edge, and the 74HC164's GND might be rising as well. Breadboards, chip carriers and long wires are not the place for fast edges.
If the 555 output is only clocking the 74HC164's CLK the faster switching of a CMOS TC555 might be better, it should pass through the logic 1 mid-level to towards V+ at least 5 times faster. The rounded droop on the CLK is strange.

"I'm planning to put the design on a PCB in the future.  Do you guys think I need to add the capacitors there as well?"

With lower impedance GNDs and a lower impedance CLK you shouldn't have to load the CLK with a cap.