Frequency compensation -- please help me understand

[TwistedTransistor]

Hi Eevblog forum

I am designing a small power supply.

When it comes to designing the frequency compensation, I can modify the open loop transfer function to ensure that the phase margin is >45 degrees (at the frequency where gain is unity).

But what about lower frequencies, where the gain is greater than unity? Do I need to care that the margin may be as little as 20 degrees, even though it never actually goes to zero?

My perhaps naive intuitive expectation was to see ringing or oscillatory behaviour, since the Nyquist stability criteria are almost met,  but I don't see anything like that. The impulse response looks fine, the output impedance looks fine.

My approach has nonetheless been to try to ensure the margin is >45 degrees for all frequencies where the gain is greater than or equal to unity. Is this really necessary? If not, why not?

Thanks for your help

[TwistedTransistor]

Here's an image of what I mean.
Phase margin is 60 degrees at 0db point. But you can see that the margin is only 16 degrees a decade earlier.
Is that a problem? It seems to have no ill effect, but I don't understand why!
Thanks!

[srb1954]

Here's an image of what I mean.
Phase margin is 60 degrees at 0db point. But you can see that the margin is only 16 degrees a decade earlier.
Is that a problem? It seems to have no ill effect, but I don't understand why!
Thanks!

(Attachment Link)

This is not a good phase response. Although the system will be stable it will likely exhibit fairly severe overshoot and ringing on any transient change. You need to further adjust your frequency compensation to maintain at least 45 degree phase margin over the whole frequency range up to the unity gain point.

You should evaluate your system in the time domain as well as the frequency domain as it is often easier to visualise the effects of changes to the compensation in the time domain. This can be done in the simulation by inserting a perturbing square wave signal into the system input and doing a transient analysis on the output.

It is also easier to check the performance of the compensation on the real hardware in the time domain by feeding in a square ware and checking the output with a scope. A good transient response will transit smoothly between levels with little or no overshoot and/or ringing.

[Kleinstein]

There is not direct problem with less phase reserve at lower frequenices, especially if significantly lower. There could be some ringing at the low frequency, but the loop gain is allready high and the ouput impedance very low so that it would be hard to excite the ringing. This is however only true in the linear range - when leaving the linear range, e.g. turn on, or hitting the current limit there can be quite some excitation / tarnsients. Worst case the circuit can show some large signal osciallation, even if stable in the linear model.

The other point to observer is that the phase reserve of the regulator depends on the load. Especially capacitive load can reduce the phase reserve. It gets essentially impossible to get >45 deg. phase reseve in all cases.

[David Hess]

In power supply design they usually recommend that the breakpoint for the compensation be a decade below the unity gain point for exactly this reason.  You can see in the slope of the response that it increases (more negative) way before the unity gain point; that right there make me think the frequency compensation is marginal at best without seeing the transient response.

[TwistedTransistor]

Thanks for your replies!

The step response is actually rock solid, no overshoot or oscillation to speak of, even once I start to add capacitive load to the output (that plot was an example of it). That's what confused me, because I was expecting to see ringing and overshoot too.

I think I am beginning to understand why. Kleinstein is right. I have no local feedback around my op amp. All my feedback is coming from the output stage. The result is that the output impedance is very very low (10 mOhm) right up to about 1kHz, so it's very hard to excite any resonance. The impedance only rises to peak at the unity gain point. Makes sense now.

I have learned a lot from this whole process and how open loop response, closed loop  response, output impedance etc all interact. It's like poking a bag of water around.

All of the material I read always talk about phase margin and sometimes gain margin, never about what happens inbetween. And as to non-linear modes I guess there is no analytical way to know what will happen, so can only do a lot of testing.

[magic]

If this response is caused by output capacitor with ESR, reducing ESR will extend the bad phase region to the right and possibly cause problems.

BTW, this is sometimes called "conditional stability". Because if you increase closed loop gain of the loop, you will have a problem, unlike with a normal opamp or similar thing.

[ocset]

But what about lower frequencies, where the gain is greater than unity? Do I need to care that the margin may be as little as 20 degrees, even though it never actually goes to zero?

I used to worry myself over this exact same thing..then i found an article by either Basso or Ridley or someone similar that said it didnt matter, and so i never worry on it now...its more important to cross over with your line going  down at , at least 10dB per decade.

[xavier60]

I'm curious to see the opening-poster's design.

[David Hess]

If this response is caused by output capacitor with ESR, reducing ESR will extend the bad phase region to the right and possibly cause problems.

That makes for a very interesting problem in output drivers for automated test equipment.  The load can be poorly defined and may or may not include a large amount of low ESR capacitance.

The solution I have seen for difficult loads is to implement the frequency compensation using *less* than -6dB/octave increasing the phase margin beyond what would normally be possible.  I can find a reference to this if anybody is interested.

[Kleinstein]

I have looked at the less than 6dB per octave slope too. The problem is that this need several internal degrees of freedom.  In the linear range this can be OK, but once it runs into saturation, it can lead to quite slow recovery.  The nonlinear part is really hard to predict and probably just simulation in the time domain is a good way to go.

Another interesting way to look at the regulator is to look at the output admittance the frequency domain. There one can directly see the effect of an added load, as the load just adds in parallel. To be sure it is stable with any reasonable passive load, the real part needs to be positive. The imaginary part can always be canceled by a capacitor (or in rare case an inductor). Similar the output impedance can be used - there needs to be some positive real part too.

[David Hess]

I am not sure what you saw but it amounts to changing the miller integrator slope which requires a resistor-capacitor network instead of a single capacitor.  It does sacrifice bandwidth but has increased phase margin because the integrator has less than 90 degrees of phase lag.