In the phase shift oscillator, does anyone think it odd that R3 and R7 are in parallel? I would expect there to be a capacitor between R3 and R4 in the printed schematic. This would allow R4 and R7 to set the bias point of the base, without interference from R3. No?
To prevent the added capacitor from interfering with the feedback phase shift, I would use 100 nF or more.
Or, remove R7 and adjust the value of R4 to give a good bias point with R3. That's probably a better solution.
I'm also concerned that the relatively high impedance of the phase shift circuit will be loaded by the relatively low input impedance of the transistor. The capacitor in the emitter leg, C4, lowers the input impedance of the transistor, potentially reducing the overall gain of the circuit to less than 1 and also affecting the phase shift of C3/R3.
The output drive at the collector of the transistor can be very low impedance. But then the phase shift network is a higher impedance. I'm not sure it can drive the input at the base, properly. Maybe increase C1, C2 and C3 to 10 nF and lower R1, R2 and R3 to 1 k. R4 will need to be adjusted to maintain the bias point, or add a larger capacitor between R3 and R4.
Maybe find another example circuit for this design.