Does jlcpbc (for the budget 4layer designs) even support blind (connects either 1:2 or 2:3 layers) or burried vias (connects layers 2:3)?
No, listed in the Drilling section.
With JLCPCB, through vias are the only option, but they don't need to be large: minimum for 4-layer design is 0.15mm diameter hole, 0.25mm diameter ring. Recommeded is 0.20mm or larger diameter hole with at least 0.15mm larger diameter ring (so 0.20mm diameter hole, 0.35mm diameter ring). EasyEda DRC defaults are way too large, so you'll need to edit your Design Rules to match.
I'm also a hobbyist, but power+signal/gnd/power+signal/gnd stackup may be even more useful, because the second power+signal plane is then sandwiched between ground planes, so you can do low coupled noise ("shielded"?) traces too.