How many resistors does I2C needs?

[chancs]

I want to get some advices on long distance I2C communication. In my design, there are 3 PCBs, 1 x  Control Board and 2x Sensor/Actuator Boards and they are interconnected by FPC cable. Which one of the following is a better solution?

Daisy Chain
Control -----(150mm)----- S/A ---(100mm)--- S/A

Star connection
Control -----(150mm)----- S/A
           |----------(300mm)---------- S/A

Another question is that how many pullup resistors do I need? I2C Clock speed is 400KHZ, Sensor/Actuator Board is quite small (50mmx30mm), and each board has 3 IC that use I2C.
I am thinking one pair of 1K2 RES on each boad would be enough.

[Bassman59]

I want to get some advices on long distance I2C communication. In my design, there are 3 PCBs, 1 x  Control Board and 2x Sensor/Actuator Boards and they are interconnected by FPC cable. Which one of the following is a better solution?

Daisy Chain
Control -----(150mm)----- S/A ---(100mm)--- S/A

Star connection
Control -----(150mm)----- S/A
           |----------(300mm)---------- S/A

Another question is that how many pullup resistors do I need? I2C Clock speed is 400KHZ, Sensor/Actuator Board is quite small (50mmx30mm), and each board has 3 IC that use I2C.
I am thinking one pair of 1K2 RES on each boad would be enough.

You only need one pullup on SCL and one pullup on SDA. Put them near your control (master) device. This way, if the FPCs get disconnected, when the master tries to access one of the devices, it won't get a response. If the bus pins float low then the master will be quite confused.

For 3.3 V systems the usual pullup is 2.2k.

[Ian.M]

I2C has two critical limits that must be respected for the bus to work.   The current that any device on the bus must sink on SDA or SCL to pull it down to logic '0' and the risetime of the SDA and SCL signals, which needs to be significantly less than 1/4 the bit rate to guarantee SDA is stable at the SCL referenced bit sampling   time points.  The least of the max logic '0' sinking currents for all devices on the bus, and the max supply voltage sets the lowest value of total (paralleled) pullup resistance you can use, and that in turn multiplied by the total bus capacitance determines the rise time and thus the fastest bit rate the bus can run at.   The bus capacitance is highly dependent on board layout and interconnects, but is usually the sum of a capacitance proportional to the total bus length plus a capacitance proportional to the number of devices on the bus.

The details and necessary calculations can be found in sections 6 & 7 of the I2C-bus specification and user manual

Your daisychain configuration is preferable if you need to minimize bus capacitance.

3x 1K2 resistors in parallel is only 400 ohms, well out of spec for any I2C devices not capable of fast mode plus (20mA sink current) operation.  As Bassman points out, you only need a single pullup, and if there is a single bus master, put it there.  In the case of a multimaster bus, you still only *NEED* a single pullup, but splitting it so there is a pullup at each master may be preferable for reliable bus fault detection.

[Doctorandus_P]

How long are your IDC calbles?
Long cables (over 20cm or so) can easily become a problem with I2C even though it can still be beaten into submission upto a few meters.

I once saw an application where I2C was used for identifying members on a backplane bus. (It may have been the Beaglebone Black)

They used I2C pullup resistors on each PCB, but relatively high value pullps. Maybe 50k or so, can't remember.
The idea was that each added PCB adds capacitance to the bus, and thus the bus needs stronger pullups.

If you use I2C you should always verify flank stiffness and signal integrity with an oscilloscope.