Electronics > Beginners
Generating precise outputs from a comparator
D-Jack:
--- Quote from: guymo on July 05, 2018, 07:25:38 pm ---D-Jack, your design has an op amp powered from 0V and 5V receiving input from 0 to -5V. Is that ok?
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It's not textbook material that's for sure :-DD. You can do it since the op-amp will saturate to its lowest voltage which is ground and there will be no damage, but a better way would be to power the op-amp like the rest and place a mosfet on the output connected to 5V. I attached a picture to illustrate
--- Quote from: guymo on July 05, 2018, 07:25:38 pm ---It seems that we're sort of reaching consensus on the right way to do the "precision output comparator" stage: either a rail to rail op amp powered from 0-5V or a MOS stage to condition the output.
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Using a mosfet allows you to be flexible when choosing op-amps since the "precision" is handled by the mosfet.
--- Quote from: guymo on July 05, 2018, 07:25:38 pm ---Thanks. That circuit will work, but I am not sure in what ways it improves on my one. I'm using non inverting stages which saves two op amps but may be less good in some ways -- are there reasons to avoid that?
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A transfer function for a non-invert amplification will add a 1 so the gain would be always (1 + x) and for many application that would be undesirable
guymo:
YES! That FET stage looks like just the sort of output conditioning I was looking for. In some sense it's the discrete version of the idea from above of inserting a CMOS IC to condition the voltage, right? I will play around with this idea.
--- Quote from: D-Jack on July 05, 2018, 07:57:12 pm ---
--- Quote from: guymo on July 05, 2018, 07:25:38 pm ---D-Jack, your design has an op amp powered from 0V and 5V receiving input from 0 to -5V. Is that ok?
--- End quote ---
It's not textbook material that's for sure :-DD. You can do it since the op-amp will saturate to its lowest voltage which is ground and there will be no damage
--- End quote ---
Some data sheets warn against damage to the device if the input goes below the lower supply voltage -- is that overly cautious? I sort of imagined there were diodes inside which would go nuts if you bring the voltage too low, but I have basically no idea about this.
--- Quote from: D-Jack on July 05, 2018, 07:57:12 pm ---
--- Quote from: guymo on July 05, 2018, 07:25:38 pm ---Thanks. That circuit will work, but I am not sure in what ways it improves on my one. I'm using non inverting stages which saves two op amps but may be less good in some ways -- are there reasons to avoid that?
--- End quote ---
A transfer function for a non-invert amplification will add a 1 so the gain would be always (1 + x) and for many application that would be undesirable
--- End quote ---
If that's the only issue you are aware of then my design is ok! The gains are definitely what I need. So the combination of that plus the FET conditioning stage could be the answer. Two op amps and a transistor -- not bad. Thanks!
rstofer:
--- Quote from: guymo on July 05, 2018, 03:14:34 pm ---
--- Quote from: D-Jack ---Ok. You can achieve this with 4 op-amp (one as summing, one as inverting with unity gain, one as comparator and one as differential), but you will need a second 5V supply or some extra circuitry to generate 5V to the comparator.
EDIT: sorry I missed the part where you said the two wave frequencies are added at the end. That will be much more complicated I'm afraid
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The frequency addition is just the result of the transfer function I am after. If the two inputs are A and B, and the output is
A + B (when 0 <= A+B < 5)
A + B - 5 (when A + B >=5)
then assuming A and B are 0-5V sawtooth waves, the output is a sawtooth whose frequency is the sum of those of A and B. So all I need to do is achieve that transfer function.
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You want to add the frequencies and get a sawtooth? Like 1V @ 100 Hz + 3V @ 300 Hz gives a 4V 400 Hz sawtooth? I'll concede I haven't actually spent any time on the time domain view of this but I don't think it really results in a sawtooth. Even if they are the same frequency, if they are out of phase the result won't be a sawtooth. If the signals line up in phase and frequency, their voltages can be added to come up with a sawtooth.
Sure, you can add voltages all day long but the result won't be a sawtooth without phase and frequency alignment.
romons:
rstofer, yes, this works. I spent a few minutes simulating it, and it really does work. You need to use an increasing sawtooth, ie, 0 up to 5 then immediately back to 0 for both of the sawtooths.
The way to think about it is the sawtooths are a line that is restarted when it hits 5, repeating again and again, similar to modulo arithmetic. Adding two lines adds the slope modulo 5, and since the slope defines the frequency, adds the frequency.
Very clever.
D-Jack:
--- Quote from: guymo on July 05, 2018, 08:14:10 pm ---YES! That FET stage looks like just the sort of output conditioning I was looking for. In some sense it's the discrete version of the idea from above of inserting a CMOS IC to condition the voltage, right?
--- End quote ---
Yes it is a discrete way to pull the input to a voltage with minimum dropout. You can achieve this with either pmos or nmos.
--- Quote from: guymo on July 05, 2018, 08:14:10 pm ---If that's the only issue you are aware of then my design is ok! The gains are definitely what I need.
--- End quote ---
Well that's the first thing but I didn't dive too deep into your circuit because I assumed you'd want the output to be equal in amplitude, that's why I set all the gains to 1. There may be some other constraints though and I would suggest you do some simulations. Upon doing one using your drawings I couldn't replicate the expected result but then again the circuit is incomplete and it may work with just two op-amps in the end.
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