Help designing serial-input 2-bit DAC

[matherp]

I'd appreciate help with what should be a simple design but one I can't get my head around.

I've got a two-wire 3.3V SPI output with a 25MHz clock. I want to pair up consecutive data bits such that I get an analogue level ( 0, 1.1V, 2.2V, 3.3V) at a frequency of 12.5MHz. The DAC output impedance can be high so a simple R2R output is fine. I need three of these for the application and to keep the component count to a minimum.

There isn't a way of getting parallel output from the uP at this speed so changing from the SPI source is not an option and of course I don't have additional signals for thing like a latch or reset input.

Any ideas gratefully received.

[matherp]

I mean't R2R as in just passive resistors - that is the easy bit it is the rest I'm struggling with

[Bassman59]

I'd appreciate help with what should be a simple design but one I can't get my head around.

I've got a two-wire 3.3V SPI output with a 25MHz clock. I want to pair up consecutive data bits such that I get an analogue level ( 0, 1.1V, 2.2V, 3.3V) at a frequency of 12.5MHz. The DAC output impedance can be high so a simple R2R output is fine. I need three of these for the application and to keep the component count to a minimum.

There isn't a way of getting parallel output from the uP at this speed so changing from the SPI source is not an option and of course I don't have additional signals for thing like a latch or reset input.

Any ideas gratefully received.

SPI isn’t two wires, it’s three at a minimum (clock, chip select, data).

Can you do I2C instead? There are many I2C “expander” chips with parallel output that you could use for your DACs.

[matherp]

Ignore the CS, it is permanently selected. There of lots of ways I could do it at lower speed but the key requirement is the 25MHz down to 12.5MHz

[Bassman59]

Ignore the CS, it is permanently selected. There of lots of ways I could do it at lower speed but the key requirement is the 25MHz down to 12.5MHz

Hopefully the DAC circuit has a reset, so at least there is an initial condition.

Without a CS, the DAC will update with every shift clock, which might not be acceptable for the application. With the CS, the rising edge can be used as an update.

[matherp]

But there isn't and can't be an active CS.

A divide by 2 off the clock can be used to latch the output for the two cycles.

Sorry if I didn't explain well enough but I have just two wires, one with a 25MHz clock and one with synchronised data. I need each pair of data levels to set an output to one of four levels for the duration of the next two clock cycles.

[mikerj]

There isn't a way of getting parallel output from the uP at this speed so changing from the SPI source is not an option and of course I don't have additional signals for thing like a latch or reset input.

Any ideas gratefully received.

If you are transmitting data continuously then it's difficult to see how this could work reliably without some kind of chip select or reset.  A single glitch on the clock will throw the TX and RX shift registers out of sync and they would never recover from that point.

If there is a delay between successive DAC updates you may be able to use something like a retriggerable monostable on the clock line to detect missing clock cycles and provide a latch signal.

[matherp]

I do have a gate every 704 clock pulses that can be used to reset but nothing more frequently

[David Hess]

Two D-flip-flops configured as a shift register can feed a 2-bit latch which is clocked at half of the clock rate to produce a 2-bit parallel output.  The shift and latch functions can be combined in a single MSI (medium scale integration) chip like an 8-bit shift register and latch while ignoring the extra bits.  The gate every 704 clock pulses can be used to maintain synchronization.