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Have I gone mad?

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--- Quote from: vxp036000 on May 01, 2012, 12:22:15 am ---The transconductance will be much lower with the source and drain interchanged.  That is, a much larger change in input voltage is required to produce the same change in output current.  And yes, I am referring to an amplifier, not a DC circuit. 

I can't really think of a legitimate reason for reversing the source and drain in a DC circuit, though.  This is, from the manufacturers perspective, an unspecified operating condition.  I haven't seen manufacturers publish reverse bias data on FETs.

--- End quote ---

It is extremely useful in synchronous rectifiers to eliminate the power wastage of the 0.7V diode drop. In buck converters that use a mosfet to replace the schottky diode to the 0v rail, this mosfet is switched on and is conducting in the reverse direction every time the main switching  mosfet to the + supply switches off.

Also it is used all the time in Mosfet-based solid state relays.


Add to that the major use, of which the SSR is just a specialist portion, being used in analogue switches.

Just about any mosfet can be used in this application, the exceptions being those with built in intelligence, either an overtemp shutdown or overvoltage/overcurrent protected ones. Any with a monitor output ( other than a current sense via a portion of the die being split out for this) are most likely not going to work well, mostly due to the parasitic diodes built into the monitoring systems.


--- Quote from: vxp036000 on May 01, 2012, 01:01:21 am ---Clever.  I learned something new :-)  I'll admit that I haven't worked much with DC circuits, aside from simple amplifier biasing schemes.  Do they recommend a particular FET for which reverse bias operation is specified?

--- End quote ---

The datasheet has a section called "External P-Channel MOSFET Transistor Selection."  It actually doesn't mention anything specific with regards to reverse bias operation.  This is for power switching so maybe power MOSFETs are more symmetrical so far as source/drain goes?  Or, maybe the reverse biasing is less of an issue since the FET will be operated in the linear region?

extremely usefull in synchronous rectification.

the mosfet as a 4 terminal device ( only accessible to people who design chips ) has no distinction between drain and source. this is why you can use them to conduct ac signals . that's how an 4066 4051 4052 4053 dg40x does it. simple mos between in and out. apply charge on the gate and off you go.

the principles governing mosfets are very simple. like charges repel, dislike charges attract. the channel is a resistive connection with two end terminals. on top of this is an isolation barrier followed by a piece of metal. this is essentially a capacitor. the channel being one plate the gate metal being the other plate and the oxide forming the dielectricum. To have a charge on a capacitor you need a voltage delta.

charge also implies 'dislike'. you cant have a 'charge' if both plates have the same level.
So , for an enhancement mode mosfet : if you apply a voltage delta across the gate capacitor ( gate sits at different potential than the channel ) you create a charge there. You have the plates at a different level , the tunnel opens (because the other plate of the gate capacitor has the opposite charge of the one i put on the gate...

hmm let me rephrase that.
n-channel enhancement mode mosfet : there are not enough electrons in the channel to conduct end to end ( electrons are negative charge carriers )
by placing a positive charge on the gate capacitor ( i pull my electrically connected plate more positive above the plate attached to the channel ) i create electrons in the channel ( i attract them there. my terminal is positive. so the other one needs be negative and electrons are 'negative' carriers. now there are enough electrons in the channel and current can flow end to end.

same with a pmos enhancement. not enough 'holes' by default. by pulling one plate of the gate capacitor negative ( applying electrons there ) i attract holes on the other plate. this creates an electrical pathway end to end in the channel.

depletion mosfets have an abundance by default ( we shoot them in during production in the doping process . this is done with an ion implanter. ) so there you need to push the charge carriers ( whether electrons or 'holes') away so they stop the conduction path in the channel.

this is why you don't see a lot of depletion mosfets: they are not very practical... lets say you want to make an inverter. this is normally done by making a totem pole of a pmos and an nmos. at powerup none of these conducts... put depletion mosfets there and you have a big fat short circuit at powerup... not very usefull. they are used in chips (where something must be 'on' by default) and for some very specialistic applications. i know two or three depletion mosses that are available as 3 pin devices.

now, a mos is a 4 pin device. there is also an electrode formed by the piece of material it is constructed in. we can't leave that floating.. because it forms another capacitor that may get charged ..... and the mos could turn on and never be turned off. so we tie this 'bulk' ( sometimes also called substrate ) to one end of the channel. Because there is a parasitic diode between bulk and channel , we now denote drain and source so people know how the parasite sits. this diode is not very good in the sense of power handling. for real power mosfets we( i always say 'we' because i work in this field. i design silicon ) actually put an extra diode on the same die and shunt it across drain-source.

here's a few tidbits of 'fun' info.

the construction of a mos is governed by length and width of the gate. make a longer gate and more electrons can cross in parallel : more current. make a wider gate and it can hold more 'pressure' : voltage when not conducting. What is width x length? : the plate size of a capacitor.
larger plates : more capacitance... that's why big fat powermosses that have large standoff voltage have higher capacitance than tiny mosfets... the plates are larger. increase current handling : capacitance goes up ( length changes ) , increase voltage blocking and capacitance goes up ( gate widens )

in the 'old days' a cmos designer would mark down how long and wide he wanted a gate to be. there was no selective implantation like today and to make a mosfet have a better channel ( lower resistance ) they needed to make it wider ( longer gate = wider channel they lay 90 degrees rotated). if you go to Intel's website and go to the museum section you can download the full schematics of the 4004 processor. they have for each transistor marked in pencil how long and wide the gate needed be.

layers were grown uniform so only length and width came into play. now we have selective implantation and we can control 'depth' ( it is actually the cross section of the channel under the gate that determines the current handling capability. for a fixed layer thickness would play with the width. with selective implantation you make the layer locally thicker.

MOSFEt : metal-oxide-semiconductor field effect transistor.
field effect i have described above : attract and repel charge on the channel.
metal oxide semiconductor denotes the construction. you have a semiconductor ( the channel ) an oxide ( the dielectricum ) and a metal ( the gate 'plate' ). for a long time there was no metal' involved. the oxide is actually conductive in the order of a few megaohms. the actual isolator is a thin barrier where the channel meets the oxide. so they were using the oxide as routing. since all you care about is 'charge' the high resistivity of the gate electrode did not matter. problem is you create an r-c filter. the c being the gate capacitor , the 'r' being the resistance of the  oxide. this bogs down how fast you can go ... for linear you don't care, for switching you do. you want to go from off to on as fast as possible. any state in-between is wasted energy.

so only later did they cover the gate oxide with metal to get charge in there quickly.

if you charge the gate capacitor you can put the mosfet away for years. pick it back up and it will still be in the state you put it in ( provided nothing discharged the gate capacitor like an esd bag or humidity ). you can do the test with an ohmmeter. measure between drain and source, put finger on gate. it will conduct. take ohmmeter away. come back tomorrow and measure again drain-source. it will still conduct.

eproms and eeproms use a floating gate. they are essentially momosfets. metal oxide metal oxide.
in discharged state that piece of metal internally does nothing. charge is attracted and 'hops' the first barrier and lands on the internal piece of metal. now the situation changes. you all of a sudden have two charged capacitors in series... that middle , floating piece, has trapped charge. remember the experiment with the ohmmeter and finger ? bingo. that's how you store it ...
you do need high voltage and you do a little bit of damage every time you make charge 'hop' across the isolating barrier ( this hopping is called tunneling : look up fowler-nordheim tunneling for the physics ). so that's why eprom and eeprom cells do wear out...

the gate of a mosfet is light sensitive. so by making the top oxide permeable to light (UV light ) you can actually discharge that floating piece of metal... and you get an uv erasable eprom. fun fact : placing charge on the gate writes '0'. that is why eproms read FF when empty ...
no charge : channel not conducting. the mos sits between ground and read line. place charge : mos turns on so read line becomes low : 0.

now all of the above is just the basics. you can play with geometries , making one end of the channel thicker than the other , different shapes of gates ( hexagons ) and this creates additional properties. some are good for switching , some good for analog some good for RF.
Finfets, Hexfets, you name it.. now we have 3d fets where the gate materiel not just lies on top but all around the channel ( as a torus around the pipe ). so these pinch off even better and faster. as opposed to stupid silicondioxide we now use hafnium based materials ( so called high-K ) because we can make much thinner dielectrics that still will still isolate well and hold charge well ( a half charged fet conducts in the ohmic region.. not good for power dissipation in the system)

when 'frying' a fet you most commonly blow a hole in the gate isolator.. you no longer have a capacitor there and it's game over ...

i could go on and on ...


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