Drive the pin high, don't use an open-drain method.
The requirement implies it's driving sequential logic i.e. flip-flops, counters, registers (type D, not merely latched), that sort of thing.
I don't know what the internal logic on those devices actually is, but it's certainly not just an IO register (latched), and the timing requirements imply something more like a state machine doing sequential processing (i.e. counting through memory addresses, etc.), versus something more general-purpose (like a mask-programmed MCU), or something more direct and high performance (like interleaved access or dual-port RAM).
There's also numerous clones of them (often with improvements like SPI, larger display support, more CGRAM etc., I don't know?) so there may be different reasons each variety uses those timing restrictions for.
Tim