Hmm, so you changed several things:
1. I see IXDN614PI instead of IR2110. These do not have an enable, so the output is always-on, no keying.
2. No twisted pairs. These should actually be more like, laminated (flex), or lots of twists in parallel, to go any distance. The '614 is capable of a
dozen amperes in a short hurry and if you expect to use any of that, you must have a low inductance path!
I have highlighted the present ground path (as best I can tell) in red:

It spreads out over the ground plane of the top board, necks down to the ground/support (dotted lines indicate path obscured by the top board), then flows around the opening where the transistors sit.
Blue shows the recommended short path, or using twisted pair (preferably star quad) instead of single-wire links.
Also, 1N4148 isn't rated for that kind of abuse; I'd recommend MBR240 or something like that.

The transformer: this looks like about half a meter of wire for the primary, is that right?
With the roughly bifilar construction, we can expect a transmission line impedance around 100 ohms, so an inductivity around 0.3 uH/m, or a total inductance (leakage between both ends of the primary) of 0.15uH. Add on another maybe 40nH for the large loop area between transistors and the center tap.
When one transistor turns on, it yanks down on its end, and this is communicated to the other side through transformer action, in series with this leakage inductance, and into its drain capacitance and snubber impedance.
Conversely when one transistor turns off, its load current instantly has nowhere to go, until communicated to the other side; the energy stored in the same inductance (i.e., drain current (at instant of turn-off) carried through the leakage inductance) must be dissipated by the transistor and snubber.
The snubber itself has some inductance, on the order of 20nH I would guess. I've never seen those capacitors before, but I'm guessing they're ceramic, and have ESL of essentially body length. The killer here is that the body is on long leads, sticking way up over the ground plane. Low inductance would be a bunch of ceramic chips in parallel, across a very wide trace (copper pour), and similarly for the resistors (which are leaded TO-220, so contribute about 5-10nH by their leads).
The snubber is still about 10nH away from the transistor itself, because the transistor's lead length is significant as well.
In total, you can draw an equivalent circuit where each transistor has ESL, then the parallel combination of them has R+L+C to ground (the snubber), then the parallel combination has leakage inductance to the opposite side transistors (which repeat the same structure), through a 1:1 transformer (the CT primary).
How much does this matter?
The transformer ratio implies a drain load around 2 ohms. The primary TLT impedance is around 100 ohms. This is a big mismatch. It may not be bad, in and of itself -- it's only a mismatch as such, at frequencies on the order of the electrical length of the primary. But this also implies we need active frequencies to be well below 100/2 times the electrical length of the primary. So, (100/2) * 0.5m = 25m electrical length, or at the speed of light in bifilar pair, about 10ns (full wave mode), or about 40ns (quarter wave mode).
By "active frequencies", I don't mean the switching frequency -- I mean the harmonics present due to switching
commutation. In other words, if the rise/fall time is around 40ns, you're likely to have problems.
Are your transistors actually 34N20? Whose "34N20"? ON Semi makes a FQ?34N20(L) but not in TO-247 package. (The FQA version is TO-3P, but that's not what's pictured.)
With optimal gate drive and values as shown, and assuming FQA34N20s, I would expect around 50ns turn-on and 10ns turn-off. This is very much in the danger zone, compared to primary leakage inductance.
We can also complete the resonant circuit between transistors -- drain capacitance rings with leakage. This is tricky because Coss varies wildly with Vds. What most likely happens is: one transistor turns off nanoseconds before the other turns on; in that time, its drain voltage hasn't risen much (because Coss is ~nF at low voltage), and the other transistor turns on, charging up the leakage inductance. Eventually, the drain voltage rises, Coss tanks (to maybe 300pF) and the drain voltage resonates at the corresponding frequency (i.e., 300pF and 190nH, or 21MHz). But because extra time is spent at low voltages, the inductance is overcharged, and this causes the peak drain voltage to be many times its linear value (if the circuit were linear (constant C), the peak would be exactly equal or less than twice the supply voltage). This will easily destroy a transistor.
One more catch on the original circuit, IR2110 pin 11 has no pull-down. So, that's not good.
I also don't get a feel for the purpose of RFC1 being so large, and C5 being so small. Is the CT intended to swing? Resonate even? That makes things even more awkward, because more voltage here means more drain voltage is possible, and that 200V rating can disappear right quickly, even with leakage and stray inductances under control.
So, I would recommend adding the ground strap indicated above, and recommend replacing the primary with a lower inductance construction, such as a star quad winding.
Star quad is a twisted quad, where opposite corners of the diamond are connected together. This gives much lower impedance (and therefore leakage) than pair does. In fact it's around half the impedance of two pairs in parallel, so it's a good synergy!
Start with 4 x 16AWG wires, preferably in two colors. Holding these in a square bundle, number them, say, 1-4 clockwise. You then have star quad connection by tying together 1 and 3, and 2 and 4. Twist about half a meter of this, and wind it around the transformer in the same four turn primary. Tie the start 1/3 to one transistor drain, the end 1/3 and the start 2/4 to the CT, and the end 2/4 to the other transistor drain.
Make this connection in the smallest length and area possible. The transistor drains themselves should be flat plates, over ground plane (this can be constructed with layers of polyester and copper foil tape, or with plates of FR-4 glued/soldered down), keeping the area minimal all the way up to the transistors. With the drain connections extended out to the CT tie point in this way, you should be able to keep loop inductance down adequately.
This should then give about 1/4th the leakage, and more like 10-20 instead of 40-60nH of stray, for a total under 60nH, a peak resonant frequency around 37MHz, and less ringing in general due to the better match. Also consider using resistors alone, for gate drive (no diode), and, a 12A driver chip isn't necessary, just a few amps will be adequate (TC4420 comes to mind; same pinout I think?). Not that that matters, since you already have the drivers, they'll just be overrated for the application.
Cheers,
Tim