Help decode/understand current source/sink generator via mirror schematic

[Houseman]

Hi forum.
I really need your help to investigate a basic analog circuit and really go under the sheets in order to understand better what is going on and maybe also help other people.
It is a pulsed constant SINK+SOURCE current generator controlled by switching ON/OFF the PNP Q1 Transistor by shorting 1Meg resistor via the Collector so, it generates both the pulsed sink and pulsed source currents at the output.
As far as I know let’s analyze the circuit:
Shorting the R4 1Meg resistor turns the Q1 ON and OFF. Is it right?
Q1 is a PNP with collector clamped to base. Diode Configuration. So the Vec will be equal to Veb and never go in saturation mode. Either off or linear region. Is it right?
Q1 is the first part of a current mirror ( I cannot see) so I_Ref1 will give a “pulsed” reference current right into the base of Q2 - Q3.

Now please give me some hints to go further… Cannot understand which way to go.
Will add some reply later after finding other steps further.
Thank You in advance for any help.. also some small hints.
Best regards

[magic]

Yes, it takes ~0.6V to pass Q1 so you have 3V across the sum of R1+R2+R5 and about 0.5mA flows through the whole stack. 0.25V is dropped across R1 and Q1 base voltage is approx. 3.6V-0.85V.

Same voltage is then applied at Ref1 to Q2 base, so there is ~0.6V Vbe at Q2 and ~0.25V across R13 and the same current flows through that pair and into the mirror at the bottom.

R14 is 4.15 times less than R so the same 0.25V across R14 would result in 4.15x more current. But the larger current also increases Q3 Vbe somewhat (~40mV IIRC) so the actual current through R14 and Q3 will be perhaps a little less than 2mA.

The bottom mirror works the same way, but here the resistor are much higher, Vbe's are almost irrelevant, and therefore the current mirror should have close to exactly 100x current gain.

All the analysis above ignores base currents, but they are small and make less than a few % difference.

[Houseman]

Thank You so much, magic.
Following Your hints made me realize that Q4 and Q5 make a so called weighted resistor current mirror, as You say the ratio between the currents entering collectors of Q4 and the one entering Q5 collector is proportional to the relative resistors on the emitters (so 100x).
By the way what I do not understand is why the circuit uses -15V voltage relative to ground.
What I also do not understand is since no current Ib is flowing into the base of Q2 (proved also with LTspice simulation) how can Q2 be held on in active region and what is its purpose.
I mean: ok that Q2 is held on since Vb relative to ground is 3.6-(0.6+0.25) > Vbe = 0.6 but I know Ic = Ib * hfe ( valid in active region). So how can, since no Ib current flows inside the base, exist a 500uA current outside collector of Q2 feeding the weighted resistor current mirror?
could I finally find a linear relation that correlates a resistor value with the final current injected and available at I_sink?
I mean: Let's see it from another perspective: globally increasing the R5 value decreases the I_sink available current. Could I find a relation between those two elements?

Thank You so much again.

[magic]

The supply has to be negative in order to sink current from a grounded load. It needs to be at least Isink1·(R16+RsinkLoad) + a few hundred mV for Q5 to work, I hope that's obvious. It doesn't need to be any more than that for the mirror to work.

There is a base current flowing through every transistor here and SPICE should show it
Whenever there is forward voltage across the BE junction, current starts to flow between E and B (like in any diode) and then it splits in 1:β proportion and part exits through the base terminal while the rest jumps to the collector. There is no way to have collector current without base current and β is rarely better than a few hundred.

The ratio of output to input really depends on current.
At very low current, voltage drop across emitter resistors is almost zero, Vbe is almost equal in both transistors and Iout=In if the transistors are identical. This ignores base current, and β can be very bad at low currents in some transistors, so Iout may even be less than Iin.
At very high current, Vbe difference is small (like, less than 0.1V for reasonable ratios) but resistor voltage is high and almost equal in both resistors, so the output/input ratio approaches the ratio of resistors. Unless the output transistor runs into its physical current limit, then it will be less.
So it's not perfectly linear.

Transistor current increases exponentially with Vbe. At room temperature it doubles for each ~20mV. Look up Ebers-Moll equation.

[Houseman]

First of all, magic, thanks again.
I too know that if no base current flows there can be no Ic current exist; I have simulated one short TURN ON phase starting from 220us, and putting a 1ohm resistor to all terminals investigated the current flowing inside Q1, Q2 Q3, please see first picture.
The reason why am I asking is because LTspice (regarding Q2 and Q3 bases receiving Iref1 current from Q1) shows that Q3 receives all the current that Q1 is "outputting" while no current to Q2 is delivered.
Please see picture 2 the other strange thing is that if you look at Ic and Ie of Q2 there are only 240uA flowing so where is the hfe multiplication factor?
Is Q2 ON??
It seems something strange to Q2 since V(N003,N006) - first graph is the Vbe voltage jumps from 490 to 590 mV and V(N003,N010) is the Vce voltage from 18.1 to 17V.
Could you have some hints?

Thanks again

[magic]

Okay, so first of all, LTspice.
If you click on the base, collector or emitter of any transistor on the schematic, it will plot that terminal's current. No need for 1Ω resistors.
If you hold the ALT key and put mouse cursor over a wire, the status bar at the bottom will display a formula which gives the total current flowing through that wire. If you then click while still holding ALT, the formula will be plotted. (And you can plot any other formula too, manually).
If a wire is named (like I_Ref1) then its name is used in plots and there is no need to worry about net numbers.

Q2 works perfectly normally. At 220µs it starts do draw a very small base current (maybe 1µA) and collector/emitter current is ~200µA. Its Vce decreases because the emitter goes down and the collector goes up, due to current flow in the resistors.

Q3 has a problem because it can't shove 2mA into a 10MΩ RsourceLoad. So what happens instead is that Vce drops to zero and all the R14 current (except for 0.3µA) exits through the base and flows into R20. So that's why the mirror operates incorrectly.

[Houseman]

Many thanks again magic: for the time, for the patience and for the hints.
Was always wrongly thinking that 1uA was equivalent to no current - BJT not working. And Ic current of 140uA was already nothing... only in the mA range was worth of interest.. 
You are right, again: originally the two I_source and I_sink legs are applied in a complementary way to the same load (470 ohm) via an external analog switch leaving the other leg floating ("flappin' in the breeze")..That's why I had connected the other leg to a 10Meg resistor.
I am anyhow more interested on the Sink state.
So some considerations to maybe clean some confusion in my head:
FOCUS on Q3 during SINK STATE:
It has floating collector: despite this, Q3 is anyway in active region (due to the voltage 3.6V - (Viref+VR14 drop) > VturnON. The Ie current 150uA is forced out the Ib despite the Ie=hfe*Ib. Kirchoff node current overbears. RIGHT?
Or is Ie current only due to the difference of the voltage drop on R14 due to Kirchoff's Voltage??

VCE drops from 5.4mV to 5.6mV since it has a terminal floating but Ve changes from 3.6 to 3.58 during OFF -> ON state.. so only PN junction (BE) is working.

Q2 is a PNP BJT. Ib current flowing outside. If it would be an NPN the IeQ3 would be injected inside base of Q2 contributing to the current boost of the mirror below. So 150uA*hfe of Q2. (picture HP1) RIGHT?
Same would be for Q1. But NOT THAT CASE. All Ib Q3, Q2 and Q1 blocks the way (or better subtract their contribution of fraction of uA to total current) so the 150uA is forced to drop across R2.
LTspice gives me IR2 = 300uA approx (150uA from IcQ1 + 150uA). in global way adding to the net current that flows outside Ic of Q1 it "depletes" the current available on the RSinkLoad boosting up the VbQ1.

So do you think that removing the sink leg would fix the circuit?
Thanks again