Overly complex AND gate.

[neo]

If control is low the signal passes through unabated and is tied to the clock input, however if control is high the output is always low. Also the 3 input NAND gates inside the white rectangle are the XOR gate.

:EDIT: Since posting this i was told that this is an AND gate so this post  is now pointless.

[bktemp]

Did i accidentally invent a new gate?

No, you just used some overcomplicated gate arrangement for a simple function.

If control is low the signal passes through unabated and is tied to the clock input, however if control is high the output is always low.

I haven't looked in detail in how your circuit works, but based on this description you can get the same functionality by using a single AND gate and inverting the control input:
When both inputs are high the output goes high otherwise it is low. So with the inverted control input, when it is low the AND gate passes the clock signal, otherwise the input stays low.

[BrianHG]

No, you just made a single 2 input AND, with 1 input, the control signal inverted.  IE going through an inverter gate.
According to your text functional description, all the gates you put together were not necessary.

IE, control = 0, through the INVERTER, feeds 1 to the AND gate.  Your other input signal, clock, if 1, the output of the AND = 1, if it is 0, output of the AND gate = 0, thus this signal is going through the AND gate 'unabated'.

If your control = 1, the INVERTER would make it 0, into the AND gate, meaning the output of the AND gate would always be 0, or low.

[neo]

Well i feel particularly stupid now but the simple fact of the matter is just throwing random ideas together i managed to make it work, and if i hadn't of built a ridiculously complex and and put it here you never could have told me it could be done with a simple AND with an inverter.

[Nusa]

Charting all the possible inputs and desired outputs makes the required logic more obvious:

Clock	Control	Output
L	L	L
L	H	L
H	L	H
H	H	L

So if the only case Output=H is when Clock=H and Control = L, you can write the equation: Output = Clock AND NOT(Control).

[amyk]

Due to propagation delays, the circuit is not exactly equivalent to the simpler version.

The floating input of the bottom middle gate is a bit worrisome too.

[neo]

Due to propagation delays, the circuit is not exactly equivalent to the simpler version.

The floating input of the bottom middle gate is a bit worrisome too.

Good catch i missed a connection in the schematic, it was drawn and posted too quickly

[james_s]

This sort of thing was not uncommon in the days of expensive TTL logic chips. If a designer had extra gates left over they would often use them as building blocks to create other types of gates rather than adding additional ICs to the design. Steve Wozniak was known for being exceptionally talented at this sort of thing.

[MrAl]

Hi,

Yes this is not exactly the same as an AND gate because of the gate delays.  This circuit would ensure that the clock signal has an effect before the control signal does because of two extra gate delays in the signal path of the control signal.  Of course then there is an extra 3 gate delays for both signals, which may or may not affect the rest of the circuit (the part we dont see).
If it is just fooling around with some gates then of course we might consider it to be similar to an AND gate.
Note that i have not checked myself to be sure it is like an AND gate not considering the gate delays, i took it for granted that the other readers determined this to be true already.