Help me understand how to program a programmable clock divider.

[MarkS]

I want to divide down a rather high clock frequency, 134.217728 MHz (2^27), down to xx frequency. I'm looking at doing so with 4 74LVC161's and 4 hexadecimal rotary switches. The LVC161's are rated up to 200 MHz, and realistically I'm looking at using frequencies lower than 100 MHz, although I could use the MC100EP016AFAG if I'm willing to pony up the $28 per chip. Regardless, the circuit is easy to design. Where I'm stuck is how to program the counters.

I found a reference to a divide-by-256 circuit using two 161's and it mentioned that it is programmed by taking the factor I want to divide by and subtracting it from 256. Using the example provided, if I wanted to divide by 183, I would subtract 183 from 256 and set the inputs of the counters to 73. What the source failed to explain is why. This is where I'm stuck.

I'm planning on using a 16-bit divider. That gives me 65,536 divisions. So, let's say that I want to divide the 134 MHz frequency to a much more reasonable 66 MHz. That would require me to divide by 2.03360193 repeating. That's a problem. 65536 - 2 is NOT 65536 - 2.03360193 repeating. Then I thought that since I have 65536 steps of division possible, if I divide 134,217,728 by 65536 I get 2048 Hz per division. If I multiply 2048 by 32,226, I get 65.998848 MHz, which is close enough. Again, however, 65536 - 32226 is NOT 65536 - 2.03360193 repeating. So... This is a dead end? 

It is clear that I lack the knowledge of the underlying processes involved to figure this out. How do I work this out? Is there a handy formula that I can use to divide a frequency by an arbitrary divisor? I do realize that there will be some error unless I'm dividing by a 2^n divisor. Still, it would be nice to be able to take an arbitrary whole number frequency between 2048 Hz and 134 MHZ and calculate a reasonably close divisor to program into the divider.

[oPossum]

I found a reference to a divide-by-256 circuit using two 161's and it mentioned that it is programmed by taking the factor I want to divide by and subtracting it from 256. Using the example provided, if I wanted to divide by 183, I would subtract 183 from 256 and set the inputs of the counters to 73. What the source failed to explain is why. This is where I'm stuck.

The counter will be reloaded with 73 when it overflows. So it counts from 73 to effectively 256 (actually overflow to 0), for a total of 183 counts per cycle.

Common methods for non-integer division are Fractional-N and DDS (direct digital synthesis).

You could do Frac-N with ordinary counter chips like the '161 or with a PLL chip. Beware of jitter!

[MarkS]

Thank you! That was what I needed. 65536 / 32226 = 2.03363743561. If the counters start at 33310 (65536 - 32226), it will be the same as dividing 134,217,728 by 2.03363743561, giving 65.998848 MHz. Assuming I understand correctly.

[Benta]

A comment on your counters: the 200 MHz specification of the 74LVC161 is in free-running mode. It is also a typical valeu, 150 MHz is guaranteed.
When you begin adding up propagation delays when reloading the counter, it will probably run at maximum 50 MHz.
And it'll get worse and worse when you start cascading counters. For a classic setup, I doubt that the chain will run at more than 10 MHz.
But using special cascading techniques (carry look-ahead), you can get the chain to run at up to 50 MHz.

You'll need an ECL prescaler to run at higher frequencies.

PS: I'll post a couple of schematics later today to show you what I mean.
PPS: Added.

[MarkS]

A comment on your counters: the 200 MHz specification of the 74LVC161 is in free-running mode. It is also a typical valeu, 150 MHz is guaranteed.
When you begin adding up propagation delays when reloading the counter, it will probably run at maximum 50 MHz.
And it'll get worse and worse when you start cascading counters. For a classic setup, I doubt that the chain will run at more than 10 MHz.
But using special cascading techniques (carry look-ahead), you can get the chain to run at up to 50 MHz.

You'll need an ECL prescaler to run at higher frequencies.

Digikey has this: https://www.digikey.com/en/products/detail/onsemi/MC10EP016FAG/918796

It operates at 1.4 GHZ max, which is FAR beyond anything I'll need. It's also an 8-bit counter, which means I need to cascade two counters instead of four and seems to be designed to be cascaded at the highest frequencies possible. $20 each, but I'm designing this for me and me alone, so if that's what I have to pay, so be it.

PS: I'll post a couple of schematics later today to show you what I mean.

Please do! I'm open to any advice.

...Beware of jitter!

That's what I found odd about the LVC161 chips. The datasheet for any other series 161, even by the same manufacturer, mention jitter when cascading. This chip did not. 

[xvr]

That was what I needed. 65536 / 32226 = 2.03363743561.

No

If the counters start at 33310 (65536 - 32226), it will be the same as dividing 134,217,728 by 2.03363743561, giving 65.998848 MHz.

If counter starts as 33310 you will get divider by (65536-333100) = 32226, not 2.... So your output frequency will be 4.16 KHz (approximately)

You need PLL to divide to such small (and not integral) amount

[Benta]

Digikey has this: https://www.digikey.com/en/products/detail/onsemi/MC10EP016FAG/918796

It operates at 1.4 GHZ max, which is FAR beyond anything I'll need.

Careful with such a sweeping statement. The maximum input clock frequency is pretty much irrelevant.
You'll need to do a precise delay/setup timing analysis to predict maximum frequency in programmable mode.

[Benta]

Also, there's no jitter in a synchronously clocked '161 counter chain. oPossum was referring to the PLL, I think.

[Terry Bites]

If it meets your spec, then go for the ECL part. Winter is here!
Is this for fun, as in beating a circuit into submission at any cost?
I ask beacuse it isn't a very rational way to create the outputs you want.
Any low cost micro can read your panel switches and set up a DDS chip or synthesiser.