Help understanding bandwidth of an amplifier

[Anthocyanina]

Hi! so lately i've been wanting to build a function generator, i've found the easiest and seemingly faster way to make one is with a raspberry pi pico someone posted an instructable for, but since the poster did everything in software and used and R2R DAC, the output of that generator wouldn't really be able to drive much, so i decided to design an amplifier for it. I have a few 2n3866 transistors from an old fm transmitter project, so i thought to use two of them for the amplifier, my idea is to have 2 stages, one common emitter to get higher voltage, and an emitter follower to be able to drive lower impedance loads. I've assumed the output of the raspberry pi to have an impedance of around 1kohm for simulation purposes since i have yet to get the raspberry pi pico, and i've simulated the amplifier on ltspice. Here is where my problem is, the transistor is specified to work at high frequencies, over 100 Mhz, and i was expecting to have at least 25 Mhz bandwidth with this amplifier, butthe ltspice simulation shows its -3db point at around 17Mhz, this would still be usable for my purpose, but i still don't understand why the cutoff is at that point and not higher, i would like to know if i'm missing something.

I understand the decoupling capacitors affect frequency response, but they would affect the lower frequencies and not the higher ones, am i getting that wrong? to test that, i also simulated the circuit without any capacitors, and the response was pretty much the same. I also changed the load to about 50 different values, and they just affect the low frequency response. in this image of the circut and the simulation results i am measuring the response at the node between c1 and r6.

The spice model i used for the 2n3866 is the model from digikey, maybe the spice parameters are wrong for the transistor? this is also something i've considered, but i still don't understand spice parameters and only see a few of them in the datasheet. Any help would be super welcome. Thank you!

[Terry Bites]

Better model http://amfone.net/Amforum/index.php?topic=27962.40;wap2.

But that's not your problem, you are not providing enough drive current. That 1k source resistance in your generator is very high compared to your base bias network, you'll need a better DAC or a buffer. A few pf of stray capacitance in your R-2R ladder will kill you stone dead above 10MHz. I'd model that before going any further. Stick to E24 resistors for sanity's sake.

[Anthocyanina]

Better model http://amfone.net/Amforum/index.php?topic=27962.40;wap2.

But that's not your problem, you are not providing enough drive current. That 1k source resistance in your generator is very high compared to your base bias network, you'll need a better DAC or a buffer. So you will need a better DAC or a buffer. A few pf of stray capacitance in your R-2R ladder will kill you stone dead above 10MHz. I'd model that before going any further. Stick to E24 resistors for sanity's sake.

Thank you! I had tried this before with no source impedance, just setting the ac value for the simulation and got similar results, also with and without decoupling capacitors. would you then recommend i maki it a 3 stage amplifier? buffer, common emitter, and another buffer? i'll also try again with that model, thank you!

[MikeK]

W2AEW, #172: Basics of Op Amp Gain Bandwidth Product and Slew Rate Limit:

[Anthocyanina]

W2AEW, #172: Basics of Op Amp Gain Bandwidth Product and Slew Rate Limit:

hi!, would this also apply to class a single transistor amplifiers? thank you!

[T3sl4co1l]

R2R DAC as in, a pile of resistors straight off GPIO pins?

Mind that these will not be very clean, both in terms of noise (you get 100% digital supply noise in the output, result depends on the quality of a power supply that may not be very quiet to begin with), and in the conversion itself (the resistors won't be matched).

Parallel DACs are cheap and plentiful, or SPI if you have the port to spare and can run it fast enough (or can accept a lower sample rate).  Highly recommended.

A DAC converts raw digital levels, to controlled reference levels.  The voltages on the R2R (if the chip uses one internally) might even be very similar, but the point is those tiny fluctuations left behind that.  And, what if anything drives them.  Might be digital noise on the supply, related to CPU activity, or USB or other peripherals; dirty external power, or ground loop noise; and it's probably not all that quiet in the first place, as voltage regulators don't need to be low noise.  The fluctuations matter, since you're doing, however many bits you are, for example if it's 8 bits or more, that's ~0.4% or less of a difference for the smallest bit.  8 bits is pretty rough for audio purposes for example, and other electrical applications will show similar results.  The one common exception I suppose being oscilloscopes, which typically only have 8 bits themselves, so won't be able to resolve finer details -- though digital filtering or high-res modes can improve things, YMMV.

As for the amplifier, and impedances -- if that's straight from GPIO pins, the rPi itself is probably closer to 50-100 ohms, but then add on the R2R resistance.  That will be the source resistance seen by the amplifier.  (Note that pin resistance causes an error in the R2R network, also limiting performance.  R2R DACs are usually designed with much larger resistors, to mitigate this error; downside, the RC time constant gets huge.)

The DAC output node's capacitance can be mitigated by shorting it out: if there's no voltage swing, there's no dV/dt for the capacitor to respond to.  That doesn't sound very useful, but we can make a virtual short circuit using a feedback amplifier.  This is the inverting op-amp configuration, or more specifically, a transresistance amplifier (resistance because its gain is Vout / Iin, trans- because the quantities measured are in different places).

A very simple transresistance amplifier can be made from a few transistors, or really even just one in common-base configuration, though the latter doesn't have any current gain so you wouldn't get much advantage just yet.  This is common design practice for DACs, back in the days when they were all R2R or current steering types -- the compliance (output voltage) range of the DAC is typically small, so that receiving it into a virtual ground node gives the least distortion and most bandwidth.

And you can always synthesize op-amps from discrete transistors, if you like; 2N3904/6 or similar jellybeans will get you 10s of MHz bandwidth even on the breadboard, and MMBTH10/81 or faster types will go higher, though you'll need to ditch the breadboard as capacitance is just too large there.

And you can always simply divide down the DAC output into a smaller resistance; this reduces the source resistance and signal level proportionally, so isn't any advantage by itself, but may be better suited to an amplifier, or to a certain amount of wiring (both cases being limited by input capacitance say, so the bandwidth goes up as the gain goes down -- the 1:1 tradeoff gives a fixed gain-bandwidth product (GBW), a figure of merit for the system).

It actually gets much better than that, or it can; when the capacitance is distributed, as in a transmission line, it is desirable to match source and/or load (at least one) to the transmission line impedance, and under this condition it will have essentially unlimited bandwidth (depending on length due to losses, or at stupid high frequencies due to waveguide modes -- 10s GHz for typical coax).  Amplifiers can be tuned in a similar way, though it takes more specialized transistors to do so; the 2N3866 and friends still have a dominant lumped-capacitance behavior, so have a fixed GBW response.

Tim

[Anthocyanina]

R2R DAC as in, a pile of resistors straight off GPIO pins?

First, thank you Tim! for all the information, that's now a lot to read about, and yes, resistors straight off the gpio pins. I considered a parallel DAC but what is on stock around here doesn't seem very useful, they only mention settling times, and none mention a settling time of less than 150ns, so it wouldn't be too useful at frequencies above around 3 MHz, if i understand correctly what the settling time is, and i really have like a 0$ budget at the moment, so even getting the raspberry pi pico is already stretching my budget for this project, which is why i decided to go with parts i already have for things like the amplifier and the power supply and the R2R network, i do have a lot of 2n2222 and 2907 transistors, so i guess i could use those for the op amp.
I'd still like to understand why even in the simulation i'm getting this unexpectedly low bandwidth with the 2n3866, and also about the same when simulating the circuit with other transistors ( 2n3904/2n2222)

Thanks again!

[Terry Bites]

I simulated it and the source resistance as expected has a dramatic effect on gain and bandwidth? My test signal is 707mv RMS (1V pk) Generator Ro=50R. Vcc 12V.
Check your results.

[Anthocyanina]

Thank you, i'll resimulate and see what i get, it seems then i'll have to add an emitter follower from the output of the R2R network to get the 50 ohm impedance into the common emitter stage 

[Terry Bites]

Its getting messy.....

[Anthocyanina]

Now i'm wondering about power, in this current design i see the DC collector current of Q3 is 63mA, and with the signal that goes in, it goes up to 80mA, so the power consumption goes from about half a watt to almost a watt, if i'm measuring the things correctly. but i'd like to know how i can calculate the power dissipation of the transistor? how much of that watt is lost as heat?  i haven't been able to find a way to calculate that easily, the emitter resistor dissipates about half a watt, is that correct? the DC operating point is 6.3V at the emitter. Thank you!

[magic]

For frequency response, Miller feedback is probably to blame. 3pF output capacitance, most of it is likely Cbc. Multiplied by stage gain it's about 10pF and time constant with 1kΩ source impedance is 10ns, giving knee at ~16MHz. Cascode should help.

All power dissipated in the transistor turns into heat, of course. You are calculating it right, Ic·Vce. This works for everything except pathological cases like 10A being forced through the BE junction. If you want to reduce Ic, increase the emitter resistor.

[Anthocyanina]

For frequency response, Miller feedback is probably to blame. 3pF output capacitance, most of it is likely Cbc. Multiplied by stage gain it's about 10pF and time constant with 1kΩ source impedance is 10ns, giving knee at ~16MHz. Cascode should help.

All power dissipated in the transistor turns into heat, of course. You are calculating it right, Ic·Vce. This works for everything except pathological cases like 10A being forced through the BE junction. If you want to reduce Ic, increase the emitter resistor.

Oh, great, thank you! i'll have to read more about the miller effect!
About the power, all power drawn is not dissipated, some of it does useful work, how can i calculate how much does actual useful work (power going into the next stage) and how much is lost as heat? my intuition tells me useful power would be v across C3 times current across C3, but that's too low, or seems too low for the power draw, it's about 12mW i think i'm doing that one wrong. for what i need this it doesn't really matter if it's efficient or not, but i started to wonder about power consumption and how hot the transistors will get and not having it clear bothers me. Thank you!

[T3sl4co1l]

Class A amplifiers typically dissipate maximum power at idle, and less under operation; the difference is the output power, which isn't much for a resistive loaded class A amplifier, so it's not very important for the most part.

Power dissipation is calculated as the average of instantaneous power V*I, for all voltage drops and current flows across the component (technically we need to sum two to get the BJT's dissipation, but we can usually ignore base power, so Ic*Vce suffices).

Or for power flow through a given branch, take the current through it, and the voltage on it (with respect to a reference node e.g. GND), multiply, and average.

Note that this includes DC power; for AC only, you need to AC-couple at least one of those input terms (V or I).  So, making this measurement with the current through the coupling capacitor, and the voltage on one side of it, gets you the signal power.

Bandwidth is determined by node capacitances and source/load resistances, give or take a modest factor for various reasons (a system with repeated poles will have -3dB somewhere below the pole frequency; or peaking networks can give a nominally flat response up to a few times higher than the RC cutoff).  The overall response is dominated by the worst case pole, of course: if your base input circuit is dropping off at 1MHz, it doesn't matter in the least that your collector output circuit is dropping off at 100MHz.

Draw the equivalent circuit, including Ccb, the hybrid-pi model of the transistor, and input and output resistances.  This demonstrates Miller effect (Cin is effectively (Vgain + 1) * Ccb), and suggests how to mitigate it (use lower Rsrc, or grounded-base, cascode or noninverting diff pair).

For impedances around a kohm, 2N3866 is rather unsuitable, with something like MPSH10 being a better fit.

Tim

[Anthocyanina]

Class A amplifiers typically dissipate maximum power at idle, and less under operation; the difference is the output power, which isn't much for a resistive loaded class A amplifier, so it's not very important for the most part.

Power dissipation is calculated as the average of instantaneous power V*I, for all voltage drops and current flows across the component (technically we need to sum two to get the BJT's dissipation, but we can usually ignore base power, so Ic*Vce suffices).

Or for power flow through a given branch, take the current through it, and the voltage on it (with respect to a reference node e.g. GND), multiply, and average.

Note that this includes DC power; for AC only, you need to AC-couple at least one of those input terms (V or I).  So, making this measurement with the current through the coupling capacitor, and the voltage on one side of it, gets you the signal power.

Bandwidth is determined by node capacitances and source/load resistances, give or take a modest factor for various reasons (a system with repeated poles will have -3dB somewhere below the pole frequency; or peaking networks can give a nominally flat response up to a few times higher than the RC cutoff).  The overall response is dominated by the worst case pole, of course: if your base input circuit is dropping off at 1MHz, it doesn't matter in the least that your collector output circuit is dropping off at 100MHz.

Draw the equivalent circuit, including Ccb, the hybrid-pi model of the transistor, and input and output resistances.  This demonstrates Miller effect (Cin is effectively (Vgain + 1) * Ccb), and suggests how to mitigate it (use lower Rsrc, or grounded-base, cascode or noninverting diff pair).

For impedances around a kohm, 2N3866 is rather unsuitable, with something like MPSH10 being a better fit.

Tim

Thank you so much Tim, that's super helpful!

[Anthocyanina]

So! today i got the raspberry pi pico and a lot of 1% resistors, which i then manually selected the ones of the same value on my multimeter, built the r2r network, the signal alone looked ok, it was a bit fuzzy but not terrible, and i connected it to the amplifier and this is what happened! i don't understand what may be causing this. It's all on a breadboard at the moment but are breadboard that incredibly terrible to cause this much distortion? i don't think so, so what may be happening here? Thank you!

[Anthocyanina]

Well! after a few days trying to figure it out, i decided to build the r2r ladder using smd resistors in as small a pcb i could, and that seems to have worked, so i guess it was a component layout problem, those through hole resistors' inductance and the breadboard's capacitance. Now with the small r2r pcb it looks really nice!