Looks right to me! It looks like I may have dumped my nearly 50 year old texts. Since nobody is dealing with discrete logic, it is not as important today. Most logic designs will be done for FPGAs or CPLDs and the synthesizer tool takes care of minimization.
It is difficult to get minimization from a truth table. You really need to get into Karnaugh Maps and there are videos all over Google. Just watch carefully how they lay out the rows and columns. This is the real way equations are minimized.