Author Topic: High Voltage/Component Footprint Question  (Read 1141 times)

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Offline insania784

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High Voltage/Component Footprint Question
« on: November 12, 2016, 09:58:32 pm »
I know that for high voltage application a certain clearance has to be maintained to prevent arcs. Knowing this why do some component footprint violate this rule? For example, this diode:
http://www.st.com/content/ccc/resource/technical/document/datasheet/34/db/51/35/8d/0b/48/54/CD00003260.pdf/files/CD00003260.pdf/jcr:content/translations/en.CD00003260.pdf.
The clearance requirement for 1200V is 6.6mm yet the distance between the pads is 2.63mm. I got my clearance requirement from, http://www.smps.us/pcbtracespacing.html.

Thanks
 

Offline Kleinstein

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Re: High Voltage/Component Footprint Question
« Reply #1 on: November 12, 2016, 10:06:53 pm »
Some parts may need potting to prevent arcing or excessive surface creep.

 

Offline Zero999

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Re: High Voltage/Component Footprint Question
« Reply #2 on: November 12, 2016, 10:36:22 pm »
I know that for high voltage application a certain clearance has to be maintained to prevent arcs. Knowing this why do some component footprint violate this rule? For example, this diode:
http://www.st.com/content/ccc/resource/technical/document/datasheet/34/db/51/35/8d/0b/48/54/CD00003260.pdf/files/CD00003260.pdf/jcr:content/translations/en.CD00003260.pdf.
The clearance requirement for 1200V is 6.6mm yet the distance between the pads is 2.63mm. I got my clearance requirement from, http://www.smps.us/pcbtracespacing.html.

Thanks
You're confusing operational requirements with safety. The diode isn't going to be used for protection against electric shock, therefore the requirements are less stringent.

Quote
OPERATIONAL REQUIREMENTS Clearance and creepage table
The distances provided by IEC and UL actually greatly exceed the spacing necessary for proper operation of the devices. This was done in order to provide increased protection against electric shock. For the circuits whose locations do not require electric shock protection, spacing between printed circuit tracks can be made smaller.

For the so called functional insulation, UL 60950-1 permits to use separation distances lesser than the specified in their charts. They just have to withstand the electric strength test (casually called Hipot) per Par.5.2.2 Table 5B. In other words, where only functional insulation is required, you don't need to meet any specific clearance between PC traces for as long as there will be no electric breakdown between them at the prescribed test voltage. The latter generally is several times greater than actual working voltage between separated traces. Unfortunately, there is no clear information in the literature on what is actual breakdown voltage between the conductors and how to design a PCB to pass a specific hipot. Experiments performed by UL in the course of analysis of silver PCB surface finish, demonstrated that the withstand voltage of a pair of parallel conductors is purely a function of the spacing, not surface finish. Based on the experiments, UL specified withstand voltage of 40 volts/mil or about 1.6 kV/mm in their UL796 Standard for Printed Wiring Boards.

The distance of 2.63mm between the pads is much greater than that required for functional insulation at 1.2kV.
 

Online T3sl4co1l

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Re: High Voltage/Component Footprint Question
« Reply #3 on: November 13, 2016, 01:44:19 am »
You can also route out under the component, so the minimum creepage path is over the component body, and that dimension remains the minimum clearance, which through air will be fine.

As Hero999 said, different standards require different levels.  One of the most common is harmonized IEC/UL 60950-1.  See:
http://www.creepage.com/
The left frame gives direction for different types of insulation requirements.  For example, grounded circuits don't need reinforced isolation to them (a single failure of the insulation results in ground fault current, clearing the fuse or breaker).

The right frame calculates the insulation required, which comes from tables in the standard (interpolated as needed and when allowed).

This still shows insufficient spacing though.  FYI, SMA/SMB/SMC (DO-214AA/B/C, not respectively) packages are quite old and have rather poor tolerances.  Manufacturers regularly recommend footprints which do not fit* their own package drawings -- probably because they know their packages are better than the standard (JEDEC DO-xx or whatever it happens to be), but probably also because they don't care much about them either.

*Fit, based on IPC recommendations for the type of solder joints used on the package.  I mean, they usually at least give a footprint that matches typical dimensions, but rarely do they give a footprint that meets or exceeds the package worst case dimensions, plus soldering fillet and tolerances.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
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