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| how arbitray waveforms are generated |
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| rstofer:
Attached is a plot of cos(x) in with 10 steps per waveform (blue with circles) and 100 steps per waveform (orange with dots). The difference is pretty noticeable. So, if you want a 1 MHz clean looking sine wave, you might want to sample at 100 MHz. You only need 100 values in the file but you have to clock pretty fast. If you are going to implement phase shifting, you simply start reading the file from some point other than t=0 and wrapping around. The MATLAB code looks like: --- Code: ---x=0:2*pi/10:2*pi; y=cos(x); plot(x,y,'-o') hold on x=0:2*pi/100:2*pi; y=cos(x); plot (x,y,'-.') ylabel('Cosine Function') legend('10 samples','100 samples') title('COS(x)') axis([0 2*pi -1.5 1.5]) shg --- End code --- [/font] The sample spacing is done here: x=0:2*pi/10:2*pi; At line 1, x is a vector starting at 0 and extending to 2*pi with intervals of 2*pi/10 or 11 samples (fence post problem). The first and last should be the same. At line 2, y is also a vector containing the cos(x) and it too has 11 values. You can see that with the blue circle at the far right end of the plot. Lines 5 & 6 do the same thing but they produce 101 samples for the orange plot. Don't have MATLAB? No problem, the code works perfectly on Octave and Octave is free. It's a very good clone of MATLAB. If you want to see the x and y values, numerically, just remove the semicolon from the end of the appropriate line (1,2,5 or 6). |
| rstofer:
--- Quote from: james_s on November 23, 2019, 07:22:10 am ---This is one of those things where if you have to ask, you're a long way from getting something workable. You generate a sawtooth like you generate any other waveform. You draw one cycle as a series of dots, the vertical position of each dot represents the value of that sample. If you want 400 MHz you have to clock the samples into the DAC at 400MHz times the number of samples, which is probably going to be 20-30 minimum. If you do the math you'll quickly see why AWGs are typically not anywhere near 400MHz. --- End quote --- Even an 80 MHz Siglent (the maximum range my budget would allow) won't produce an 80 MHz square wave, 25 MHz is as far as it goes. I guess they don't implement it as a simple step function in the middle of the period. That SDG2082X is $619 plus shipping so AWGs get pretty expensive even for low frequencies. It samples at 1.2GSa/s There is a lot of educational material re: the Analog Discovery 2 over at Digilent. They talk about the AWG and how it is implemented. It is only 12 MHz bandwidth with 100 MSa/s sampling: See Section 3 here: https://reference.digilentinc.com/reference/instrumentation/analog-discovery-2/reference-manual I'm pretty sure 400 MHz sounds neat when you write it down but I'm not sure it is realizable by mere mortals. With a 1 GSa/s rate, there would only be 2.5 samples per waveform. I didn't produce a plot like that but it would be pretty hideous. |
| rstofer:
--- Quote from: joeqsmith on November 23, 2019, 05:58:22 pm --- Fun times. I constructed an engine simulator and needed to have different waveforms for the various sensors. I wanted to be able to control the frequency as well as AM and FM modulate so I used an FPGA to do everything. --- End quote --- I like analog computing and simulating the suspension of a vehicle (at least one front tire) is a classic problem since it is essentially a mass-spring-damper problem and those are well understood. But what if the ground under the tire contains a chuck-hole? I have toyed with the idea of using an AWG to generate the surface. I could do this quite easily with the Analog Discovery 2. I could even model those nefarious speed bumps! Other than sheer laziness, I don't know why I haven't done it yet. AWGs could be a lot of fun to play with but I'm just guessing that the frequency is going to be a whole lot less than 400 MHz. For my suspension project, even the 12 MHz bandwidth of the Analog Discover 2 is FAR more than required. Nothing on the chassis is working in microsecond time scales. If it does, I guess we move to Euler's Method. |
| rstofer:
When creating the sample file, there would be a tendency to want to use ASCII representations of the values. Simply, these are user readable values. At some point, there needs to be logic in the FPGA to read the file, convert the values to binary and store them in a samples table in BlockRAM. It might be worth creating a small CPU core because there will be more to do than just read values. There will be some kind of UI (switches, knobs and dials). I suppose the core might as well be the Xilinx MicroBlaze since there is a set of tools for writing code in C and so forth. Generating the signal, that is, stepping through BlockRAM, grabbing the values and stuffing them into the DAC is the easiest part of the job. Coming up with a highly variable sample clock is going to be a challenge. The alternative is to use a very fast sample clock but that implies a LOT of samples for slow signals. A 1 Hz signal with a 1 GHz sample clock is going to need a billion samples. Yup! Generating the sample clock for various realizable signals and speeds is going to be a bit of work and some arithmetic. |
| gf:
--- Quote from: rstofer on November 23, 2019, 06:28:26 pm ---Coming up with a highly variable sample clock is going to be a challenge. The alternative is to use a very fast sample clock but that implies a LOT of samples for slow signals. --- End quote --- "Classical" DDS generators are usually based on a fixed (fast) clock. [ Some commercial AWGs use more sophisticated algorithms, though, than plain DDS, in order to overcome some limatations of DDS. ] --- Quote ---A 1 Hz signal with a 1 GHz sample clock is going to need a billion samples. --- End quote --- Not really a problem, though. Just spend a sufficient number of bits for the DDS generator's accumulator and you can even generate sub-Hz signals. You don't need a waveform memory which can store a billion samples, but it can be much smaller (-> keyword "phase truncation"). gf |
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