how are mosfet gates driven on a CMOS IC

[bockpa]

Hello,
  I am curious how CMOS chips are designed.  Do they have onboard charge pumps to drive the gates of the mosfets on a CMOS chip? 

  I have been playing with driving MOSFETs.  Specifically N channel enhancement mode MOSFETs.  I work with 5V digital chips such as 5V arduinos.  Driving the gates of power mosfets typically requires providing 10v about the source terminal.  I have experimented with making diode-capacitor charge-pumps, voltage multipliers.  And this works to drive power mosfets. 

  I have also experimented with using mosfet driver IC's.  But there is a part of me that thinks that is cheating.  I really like to know how this stuff works from discrete parts.

  But there are times when I want my arduino to drive smaller mosfets and that gets me into the logic-level mosfets.  But then you work on a 3.3v project, and you are back to mosfet drivers. 

  So with all this "difficulty" in driving mosfets well, how do they do it on a CMOS chip?  Possibly the answer lies in that the mosfets are even weaker within the chip itself, as possibly the current they flow is mostly to charge or discharge another mosfet in the circuit.  Please help set me straight regarding this issue.  And are these kinds of really weak mosfets available as a discrete part, or are they so small they are very sensitive to esd and can only live within the diode clamped environment of the IC itself? 

[bockpa]

I get that the gate charge limits are controlled by the dielectric strength of the insulator in gate and the thickness of the insulator.  But is there a reason why so many mosfets have +/- 20v gate voltage limits and are typically saturated at 10V?  Or is it just because it is good to standardize on something. 

I have found it difficult to get an answer to these questions, and I hope someone in-the-know can help me improve my understanding of this.

On a possibly related side note, when chip manufacturers refer to a particular process, such as 45nm process, what is the 45 nanometers measuring?  is it the gate thickness?

[T3sl4co1l]

Low voltage (under 30V) MOSFETs require less gate voltage to achieve solid "on" and "off" states, too.

A lot of new gate drive ICs use dual N-channel output stages, and indeed, the chip integrates a charge pump to drive this.  For all the back-end logic, and pretty much everything else under the sun, CMOS is used.

On a possibly related side note, when chip manufacturers refer to a particular process, such as 45nm process, what is the 45 nanometers measuring?  is it the gate thickness?

Feature size, either the minimum line width/space or the tolerance of an edge (between a line and a space).  I forget which exactly, I'm afraid.

The result is that a transistor takes up several times the feature size, because trenches are needed to isolate around it, and the source, channel and drain have to be formed, etc.

The gate oxide thickness is unrelated to the feature size, because it's a vertical height created by planar chemical process, not by optical projection (which is the limiting factor on feature size).

Tim

[radiogeek381]

Hello,
  I am curious how CMOS chips are designed.  Do they have onboard charge pumps to drive the gates of the mosfets on a CMOS chip? 

If you are asking about microprocessors and larger logic CMOS widgets, here's a brief overview.

All the circuits are built around NMOS and PMOS devices.  The simplest CMOS gate is an inverter.  It has one NMOS device and one PMOS device.

• The gates of the NMOS and PMOS devices are tied to the input.
• The drains of the NMOS and PMOS devices are tied to the output
• The source of the NMOS device is connected to VSS (a culturally embedded name for "local ground")
• The source of the PMOS device is connected to VDD (a very embedded name for "the upper supply rail") at 3.3V.

For a 3.3V device the NMOS threshold voltage might be something like 0.7V and the PMOS threshold -0.7V. (More modern processes that run at 1.0V or even lower have very low threshold voltages.)

That means that the NMOS device turns on when its gate-source voltage rises above 0.7V.  So if the input is pulled all the way to the upper rail, the NMOS device is really really on.  The PMOS device will be cut off.  The output will be pulled to ground.

If we pull the input down, then the PMOS device will begin to turn on, and the NMOS device will start to turn off.  Eventually when the input gets to the lower rail, the PMOS pullup is really really on and the NMOS pulldown is cutoff.

NOR gates and NAND gates have slightly different topologies (for one thing, they each have two or more inputs).  There are even more complex configurations, but most of the area on a die is taken up with pretty simple circuits.  (Though a RAM cell is way more complicated than they tell you about in school....) 

There was a time when really hot CMOS designers drew transistor level schematics.  In the microprocessor industry, those days are pretty much gone.  There are a few lonely holdouts, but most CMOS logic design is mediated by a logic synthesis process that translates descriptions in verilog or VHDL into netlists and layout.

The feature size number (like 45nm) used to correlate very closely with the length of a channel.  So in a 250nm process, a typical inverter would be built with an NMOS device whose gate was 250nm long and 2500 nm wide.  The PMOS device would have a gate dimension of 250nm long by 5000nm wide.  Back then, the length of the channel was long enough that the 2x difference in electron mobility vs. hole mobility made a big difference.  Modern processes with their very short channels have mitigated this difference a great deal.

So, no, there are no charge pumps to jack the gate up.  But there was a time when microprocessors were designed with just one type of device -- many were NMOS only, others PMOS only.  For NMOS only circuits, it is hard to get the gate all the way to the rail. (I won't go into why that's important, but it is, for certain kinds of circuits.)  In those circuits there is a kind of charge pump called a "bootstrap" invented by Rueben Joynson at GE back in the late sixties or early seventies.  But that isn't used today for silicon circuits. 

Note that the above description is a simplification.  Things are different with output drivers and input receivers.  Connecting to an external contact creates lots of circuit issues that the interior circuit designers can safely ignore.  Additionally, circuits like DRAM cells, SRAM cells, sense amplifiers, flip-flops, and latches often have circuit topologies that are far more complex than the simple switch network of a NAND gate.  High performance, or low power, or high reliability designs also need to account for lots of effects and aspects of wires -- lateral coupling capacitance between wires, for example.  There are even cmoplex "wear out" mechanisms that big league chip designers take into account.


I hope this was helpful.  For a view of CMOS design circa 1990, I can highly recommend Dobberpuhl and Glasser "The Design and Analysis of VLSI Circuits" it may seem quaint in light of today's 14nm CMOS processes, but it was a great book back then...

[bockpa]

Thanks Radiogeek.  I changed jobs after I posted my questions and just recently rediscovered my post.  I appreciate your reply.  finally received.