how bad practice is it to route traces inside a QFN?

[JPortici]

Board preview:


This is my first four layer board (detail not really relevant, just wanted to share the moment), layer stackup is TOP - GND - 3V3 - BOTTOM (switching regulator on top layer)
5V - Blue
3V3 - Green
GND - Orange

This is also going to be my most dense board to date, dimensions are 40x18mm, components on both sides.
I can't make it any taller, and i'm worried i'll have to cut 0.5-1mm.

As you should be able to see, some of the traces on the MCU (big QFN chip in the middle) are drawn inside and then moved to another layer.

How bad that could turn out?

I'm relying on the fact that, according to the datasheet, on the MCU (PIC32MK0512GPE064) the exposed pad is about as half as complete package size: 9x9mm QFN, EP is 5.5x5.5mm max, so i used a pattern that had a 5.5mm EP.
However, the recommended land pattern suggests to use an EP as big as possible (7.35x7.35 mm). I suppose a bigger pad is used so that it retains the excessive paste while soldering the chip?

Current datasheet: http://ww1.microchip.com/downloads/en/DeviceDoc/60001402D.pdf (package description at page 671)

[alexanderbrevig]

I've done this. I used tented vias for the traces and a smaller aperture for the smaller-than-recommended thermal pad. For me it worked at least 

EDIT: Though seems most of those traces could be placed outside? Your decoupling also looks a bit weird. I know there's a discussion on here somewhere if you should go from VCC via the CAP to the PAD. Instead of VCC-PAD-CAP as you do for yours.

[djnz]

I've done similar things, board turned out fine. This part of the board was all-digital though (no ADC / DAC signals).

[JPortici]

I've done this. I used tented vias for the traces and a smaller aperture for the smaller-than-recommended thermal pad. For me it worked at least 

EDIT: Though seems most of those traces could be placed outside? Your decoupling also looks a bit weird. I know there's a discussion on here somewhere if you should go from VCC via the CAP to the PAD. Instead of VCC-PAD-CAP as you do for yours.

yeah, the problem is that you are seeing only one layer, on the other side there are other components and traces. the other side is a bluetooth module (occupying about half the space) a linear regulator and most of the decoupling.
Decoupling should indeed be VCC-CAP-PAD, i didn't forget about it. I'll do my best rearrange some traces but for some i don't think i will be able to.

So tented Vias should be the answer i'm looking for

[mikeselectricstuff]

Unless it's for thermal or RF reasons, you often don't need to connect the pad on a QFN ( check the datasheet).
I've never used the pad on QFN PICs. Also makes rework a lot easier.

I do try to avoid vias under unused pads though, in case a sliver of copper pierces the resist - I may be being over-cautious.
If the PCB has silkscreen I may put a silkscreen pad as an addtional layer between thr QFN pad and tracks underneath

[JPortici]

Unless it's for thermal or RF reasons, you often don't need to connect the pad on a QFN ( check the datasheet).
I've never used the pad on QFN PICs. Also makes rework a lot easier.

I do try to avoid vias under unused pads though, in case a sliver of copper pierces the resist - I may be being over-cautious.
If the PCB has silkscreen I may put a silkscreen pad as an addtional layer between thr QFN pad and tracks underneath

that's brillant!

and you are right about the pad

The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.

Most parts i use with an exposed pad are RF and regulators so i automatically put a lot of vias.
I wouldn't remove them though because even if the pad is not connected to VSS, all the VSS pins were connected to the pad and then to the plane. But I may remove some of them for easier rework

[mikeselectricstuff]

Oh, and I did this once.....
Not proud but makes sense when you see the other side