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How do I implement ESD protection for a voltage reference?

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Brak:

--- Quote from: imo on August 12, 2018, 03:09:20 pm ---Are there any rules how to set the capacity of the Wima cap for the ESD protection?

--- End quote ---

I'm certainly no expert, don't take my advice.

I've always assumed, without really thinking about it, the larger the capacitance the better within whatever limits the reference will drive.  And that several capacitors of different values and perhaps different technologies, having different resonant frequencies, would be better than a single capacitor.  I guess I'm assuming this counts as a bypass capacitor.

Our host has a YouTube video, "Bypass Capacitor Tutorial" at:

 

I think Dave says towards the end of the video that it's really hard to be sure what's happening without a lot of expensive equipment.

Brak

Andreas:
Hello,

the picture is only a theoretical one.
Practically (when using capacitors of the same type) the minimum ESR is lower with larger capacity value.
So the "advantage" of using a lower capacity value at higher frequencies is much smaller than in Daves diagram.

Especially when using a bypass capacitor and if you take in account that from capacitor to the chip of the integrated cirquit are at least 5 mm (0.2") lead length = inductor of 5 nH.
So if you look at the effective impedance which is seen from the chip it is all the same regardless of the capacitor above the self resonant frequencies.

With best regards

Andreas

T3sl4co1l:
Dave misses the problem with paralleling capacitors: each time two curves cross, there is a peak where impedance goes up.  The amount it goes up by, is symmetrical with the amount it goes down by.  The centerline both amounts are relative to is the resonant impedance Zo = sqrt(L/C).  One resonance is series mode, with a minimum impedance of ESR, and a Q of Zo / ESR.  The other is parallel mode, with a maximum impedance of Zo * Q.

This is why it's more critical to have a well damped supply.

Tim

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